- 06 10月, 2020 1 次提交
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由 Yongqiang Sun 提交于
[Why] enable ODM on eDP panel with ABM will result in color difference on the panel due to only one ABM module to set one pipe. [How] Block ABM in case of ODM enabled on eDP. Signed-off-by: NYongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: NEric Yang <eric.yang2@amd.com> Acked-by: NEryk Brol <eryk.brol@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 23 9月, 2020 1 次提交
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由 Peikang Zhang 提交于
[Why] We dont's turn off backlight before power off eDP (VDD), which is a violation of eDP specs. [How] Power off eDP backlight before power off eDP Signed-off-by: NPeikang Zhang <peikang.zhang@amd.com> Reviewed-by: NAnthony Koo <Anthony.Koo@amd.com> Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 16 9月, 2020 1 次提交
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由 Aric Cyr 提交于
Disable triplebuffering by default. Signed-off-by: NAric Cyr <aric.cyr@amd.com> Acked-by: NAurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 18 8月, 2020 1 次提交
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由 Qingqing Zhuo 提交于
[why] Current pipe merge and split logic only supports cases where new dc_state is allocated and relies on dc->current_state to gather information from previous dc_state. Calls to validate_bandwidth on UPDATE_TYPE_MED would cause an issue because there is no new dc_state allocated, and data in dc->current_state would be overwritten during pipe merge. [how] Only allow validate_bandwidth when new dc_state space is created. Signed-off-by: NQingqing Zhuo <qingqing.zhuo@amd.com> Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 11 8月, 2020 3 次提交
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由 Daniel Kolesa 提交于
This adds ARM64 support into the DCN. This mainly enables support for Navi graphics cards. The dcn10 changes haven't been tested, since I don't have the relevant hardware available, but there is no way to conditionally disable them, so I've done them anyway. Signed-off-by: NDaniel Kolesa <daniel@octaforge.org> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alvin Lee 提交于
[Why] When changing pixel formats for HDR (e.g. ARGB -> FP16) there are configurations that change from 2 pipes to 1 pipe. In these cases, it seems that disconnecting MPCC and doing a surface update at the same time(after unlocking) causes some registers to be updated slightly faster than others after unlocking (e.g. if the pixel format is updated to FP16 before the new surface address is programmed, we get corruption on the screen because the pixel formats aren't matching). We separate disconnecting MPCC from the rest of the pipe programming sequence to prevent this. [How] Move MPCC disconnect into separate operation than the rest of the pipe programming. Signed-off-by: NAlvin Lee <alvin.lee2@amd.com> Reviewed-by: NAric Cyr <Aric.Cyr@amd.com> Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alvin Lee 提交于
[Why] Caused pipe split regression Signed-off-by: NAlvin Lee <alvin.lee2@amd.com> Reviewed-by: NAric Cyr <Aric.Cyr@amd.com> Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 07 8月, 2020 1 次提交
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由 Reza Amini 提交于
[Why] Each asic can optimize best based on its capabilities [How] Optimizing timing for a new pixel clock Signed-off-by: NReza Amini <Reza.Amini@amd.com> Reviewed-by: NAnthony Koo <Anthony.Koo@amd.com> Acked-by: NEryk Brol <eryk.brol@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 05 8月, 2020 2 次提交
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由 Rikard Falkeborn 提交于
The only usage of dcn21_res_pool_funcs is to assign its address to a const pointer. Make it const to allow the compiler to put it in read-only memory. Signed-off-by: NRikard Falkeborn <rikard.falkeborn@gmail.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alvin Lee 提交于
[Why] When changing pixel formats for HDR (e.g. ARGB -> FP16) there are configurations that change from 2 pipes to 1 pipe. In these cases, it seems that disconnecting MPCC and doing a surface update at the same time(after unlocking) causes some registers to be updated slightly faster than others after unlocking (e.g. if the pixel format is updated to FP16 before the new surface address is programmed, we get corruption on the screen because the pixel formats aren't matching). We separate disconnecting MPCC from the rest of the pipe programming sequence to prevent this. [How] Move MPCC disconnect into separate operation than the rest of the pipe programming. Signed-off-by: NAlvin Lee <alvin.lee2@amd.com> Reviewed-by: NJun Lei <Jun.Lei@amd.com> Acked-by: NAurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 31 7月, 2020 1 次提交
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由 Reza Amini 提交于
[Why] Each asic can optimize best based on its capabilities [How] Optimizing timing for a new pixel clock Signed-off-by: NReza Amini <Reza.Amini@amd.com> Reviewed-by: NAnthony Koo <Anthony.Koo@amd.com> Acked-by: NEryk Brol <eryk.brol@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 22 7月, 2020 2 次提交
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由 Igor Kravchenko 提交于
[Why] Implement an interface to obtain plane size caps [How] Add min_width, min_height fields to dc_plane_cap structure. Set values to 16x16 for discrete ASICs, and 64x64 for others. Signed-off-by: NIgor Kravchenko <Igor.Kravchenko@amd.com> Reviewed-by: NAric Cyr <Aric.Cyr@amd.com> Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Aurabindo Pillai 提交于
[Why] dcn20_add_dsc_to_stream_resource is accessed in amdgpu_dm directly. This creates build error for configuration with DCN disabled. [How] Make the function available through a resource pool function so that dcn20 function need not be called directly. Signed-off-by: NAurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 15 7月, 2020 1 次提交
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由 Sung Lee 提交于
[WHY] In headless systems, if set mode is not called, hardware will not be powered down on boot, causing HW/SW discrepancies. Powering down hardware on boot will ensure SW state is accurate. [HOW] Set a timer callback on boot for 10 seconds. If set mode is not called within that time, power down hardware. Otherwise, do not power down. Signed-off-by: NSung Lee <sung.lee@amd.com> Reviewed-by: NAnthony Koo <Anthony.Koo@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 01 7月, 2020 4 次提交
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由 Wenjing Liu 提交于
[why] DP link layer CTS specs updated to change the test parameters in test 4.2.1.1. Before it requires source to delay 400us on aux no reply. With the specs updates Errata5, it requires source to delay 3.2ms (based on LTTPR aux timeout) This causes our test to fail after updating with the latest test equipment firmware. [how] the change is to allow LTTPR 3.2ms aux timeout delay by default. And set back to 400us if LTTPR feature is not enabled. We will set 3.2ms and always enable LTTPR non transparent mode if LTTPR feature is enabled and LTTPR is present. Signed-off-by: NWenjing Liu <wenjing.liu@amd.com> Reviewed-by: NJun Lei <Jun.Lei@amd.com> Acked-by: NKrunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Aurabindo Pillai 提交于
[Why & How] DMUB command table should be allowed to be used only if dmcu is explicitly disabled. Signed-off-by: NAurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Wenjing Liu 提交于
[why] The change causes some regression in a common use case. Will need more investigation before fixing the original issue. [how] This reverts commit fb8cf277. Signed-off-by: NWenjing Liu <wenjing.liu@amd.com> Reviewed-by: NJun Lei <Jun.Lei@amd.com> Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Roman Li 提交于
[Why] SOC_BOUNDING_BOX_VALID is unused and not required for dcn21. [How] Remove it. Signed-off-by: NRoman Li <Roman.Li@amd.com> Reviewed-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 29 5月, 2020 2 次提交
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由 Yongqiang Sun 提交于
[Why] dal side nv12 wa has a lot of side effects. KMD side wa is used, so this should be remove. [How] Removed wa from dal side. Signed-off-by: NYongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: NTony Cheng <Tony.Cheng@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Yongqiang Sun 提交于
[Why & How] Implement abm set_pipe call stacks Have some asics speicifc call stacks for abm. Signed-off-by: NYongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: NAnthony Koo <Anthony.Koo@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 22 5月, 2020 2 次提交
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由 Dmytro Laktyushkin 提交于
Save the correct num vmid during resource creation and fix RN gpuvm level from 1 to 16 vmid entries. Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: NEric Bernstein <Eric.Bernstein@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Nicholas Kazlauskas 提交于
[Why] We dropped the delay after changed the cursor functions locking the entire pipe to locking just the CURSOR registers to fix page flip stuttering - this introduced cursor stuttering instead, and an underflow issue. The cursor update can be delayed indefinitely if the cursor update repeatedly happens right around VUPDATE. The underflow issue can happen if we do a viewport update on a pipe on the same frame where a cursor update happens around VUPDATE - the old cursor registers are retained which can be in an invalid position. This can cause a pipe hang and indefinite underflow. [How] The complex, ideal solution to the problem would be a software triple buffering mechanism from the DM layer to program only one cursor update per frame just before VUPDATE. The simple workaround until we have that infrastructure in place is this change - bring back the delay until VUPDATE before locking, but with some corrections to the calculations. This didn't work for all timings before because the calculation for VUPDATE was wrong - it was using the offset from VSTARTUP instead and didn't correctly handle the case where VUPDATE could be in the back porch. Add a new hardware sequencer function to use the existing helper to calculate the real VUPDATE start and VUPDATE end - VUPDATE can last multiple lines after all. Change the udelay to incorporate the width of VUPDATE as well. Signed-off-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: NAric Cyr <Aric.Cyr@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 21 5月, 2020 1 次提交
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由 Nicholas Kazlauskas 提交于
[Why] We dropped the delay after changed the cursor functions locking the entire pipe to locking just the CURSOR registers to fix page flip stuttering - this introduced cursor stuttering instead, and an underflow issue. The cursor update can be delayed indefinitely if the cursor update repeatedly happens right around VUPDATE. The underflow issue can happen if we do a viewport update on a pipe on the same frame where a cursor update happens around VUPDATE - the old cursor registers are retained which can be in an invalid position. This can cause a pipe hang and indefinite underflow. [How] The complex, ideal solution to the problem would be a software triple buffering mechanism from the DM layer to program only one cursor update per frame just before VUPDATE. The simple workaround until we have that infrastructure in place is this change - bring back the delay until VUPDATE before locking, but with some corrections to the calculations. This didn't work for all timings before because the calculation for VUPDATE was wrong - it was using the offset from VSTARTUP instead and didn't correctly handle the case where VUPDATE could be in the back porch. Add a new hardware sequencer function to use the existing helper to calculate the real VUPDATE start and VUPDATE end - VUPDATE can last multiple lines after all. Change the udelay to incorporate the width of VUPDATE as well. Signed-off-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: NAric Cyr <Aric.Cyr@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 06 5月, 2020 1 次提交
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由 Yongqiang Sun 提交于
[Why] panel_cntl specific register should be access in panel_cntl object. [How] Move these register access from abm to panel_cntl. Signed-off-by: NYongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: NAnthony Koo <Anthony.Koo@amd.com> Acked-by: NAurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 01 5月, 2020 2 次提交
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由 Zou Wei 提交于
Fixes coccicheck warning: drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c:1398:60-61: WARNING: Unsigned expression compared with zero: j >= 0 Fixes: 23838777 ("drm/amd/display: fix rn soc bb update") Reported-by: NHulk Robot <hulkci@huawei.com> Signed-off-by: NZou Wei <zou_wei@huawei.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Jason Yan 提交于
Fix the following coccicheck warning: drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c:31:51-52: exit_optimized_pwr_state: first occurrence line 86, second occurrence line 92 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c:31:51-52: optimize_pwr_state: first occurrence line 85, second occurrence line 91 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c:31:51-52: set_cursor_attribute: first occurrence line 71, second occurrence line 89 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c:31:51-52: set_cursor_position: first occurrence line 70, second occurrence line 88 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c:31:51-52: set_cursor_sdr_white_level: first occurrence line 72, second occurrence line 90 Signed-off-by: NJason Yan <yanaijie@huawei.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 29 4月, 2020 9 次提交
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由 Aric Cyr 提交于
[Why] Current locking scheme for cursor can result in a flip missing its vsync, deferring it for one or more vsyncs. Result is a potential for stuttering when cursor is moved. [How] Use cursor update lock so that flips are not blocked while cursor is being programmed. Signed-off-by: NAric Cyr <aric.cyr@amd.com> Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: NAurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Sung Lee 提交于
[WHY] The downspread percentage was copied over from a previous version of the display_mode_lib spreadsheet. This value has been updated, and the previous value is too high to allow for such modes as 4K120hz. The new value is sufficient for such modes. [HOW] Update the value in dcn21_resource to match the spreadsheet. Signed-off-by: NSung Lee <sung.lee@amd.com> Reviewed-by: NYongqiang Sun <yongqiang.sun@amd.com> Acked-by: NAurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Dmytro Laktyushkin 提交于
Currently RN SOC bounding box update assumes we will get at least 2 clock states from SMU. This isn't always true and because of special casing on first clock state we end up with low disp, dpp, dsc and phy clocks. This change removes the special casing allowing the first state to acquire correct clocks. Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: NEric Yang <eric.yang2@amd.com> Acked-by: NAurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: NTony Cheng <Tony.Cheng@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Aric Cyr 提交于
[Why] Current locking scheme for cursor can result in a flip missing its vsync, deferring it for one or more vsyncs. Result is a potential for stuttering when cursor is moved. [How] Use cursor update lock so that flips are not blocked while cursor is being programmed. Signed-off-by: NAric Cyr <aric.cyr@amd.com> Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: NAurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Krunoslav Kovac 提交于
[Why&How] modules/color calculates various colour operations which are translated to abstracted HW. DCE 5-12 had almost no important changes, but starting with DCN1, every new generation comes with fairly major differences in color pipeline. We would hack it with some DCN checks, but a better approach is to abstract color pipe capabilities so modules/DM can decide mapping to HW block based on logical capabilities, Signed-off-by: NKrunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by: NAric Cyr <Aric.Cyr@amd.com> Acked-by: NAnthony Koo <Anthony.Koo@amd.com> Acked-by: NAurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Yongqiang Sun 提交于
[Why & How] Add set backlight to hw sequencer, dmu communication will be handled in hw sequencer for new asics. Signed-off-by: NYongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: NAnthony Koo <Anthony.Koo@amd.com> Acked-by: NAurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Nicholas Kazlauskas 提交于
[Why] We read memory that we shouldn't be touching if the struct isn't a full union dmub_rb_cmd. [How] Fix up all the callers and functions that take in the dmub_cmd_header to use the dmub_rb_cmd instead. Signed-off-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: NTony Cheng <Tony.Cheng@amd.com> Acked-by: NAurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Sung Lee 提交于
[WHY] The downspread percentage was copied over from a previous version of the display_mode_lib spreadsheet. This value has been updated, and the previous value is too high to allow for such modes as 4K120hz. The new value is sufficient for such modes. [HOW] Update the value in dcn21_resource to match the spreadsheet. Signed-off-by: NSung Lee <sung.lee@amd.com> Reviewed-by: NYongqiang Sun <yongqiang.sun@amd.com> Acked-by: NAurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Dmytro Laktyushkin 提交于
Currently RN SOC bounding box update assumes we will get at least 2 clock states from SMU. This isn't always true and because of special casing on first clock state we end up with low disp, dpp, dsc and phy clocks. This change removes the special casing allowing the first state to acquire correct clocks. Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: NEric Yang <eric.yang2@amd.com> Acked-by: NAurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: NTony Cheng <Tony.Cheng@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 23 4月, 2020 3 次提交
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由 Anthony Koo 提交于
[Why] it doesn't represent panel specifically, it's more like the control logic for the panel [How] change from panel to panel cntl to make it a bit more clear Signed-off-by: NAnthony Koo <Anthony.Koo@amd.com> Reviewed-by: NTony Cheng <Tony.Cheng@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Anthony Koo 提交于
[Why] panel power sequencer is currently just sitting in hwseq but it really it tied to internal panels [How] make a new panel struct to contain power sequencer code Signed-off-by: NAnthony Koo <Anthony.Koo@amd.com> Reviewed-by: NTony Cheng <Tony.Cheng@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Dale Zhao 提交于
[Why]: Renoir's pipe VM flags are not correctly updated if pipe strategy has changed during some scenarios. It will result in watermarks mistakenly calculation, thus underflow and garbage appear. [How]: Correctly update pipe VM flags to pipes which have been populated. Signed-off-by: NDale Zhao <dale.zhao@amd.com> Signed-off-by: NSung Lee <sung.lee@amd.com> Reviewed-by: NYongqiang Sun <yongqiang.sun@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 09 4月, 2020 2 次提交
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由 Wenjing Liu 提交于
[why] When display is connected with a native DP port, DP2 mode register value is a don't care. Driver mistakenly reduce max supported lane count to 2 lane based on the don't care value. [how] Add additional check only if USB C DP alt mode is enabled, we will determine max lane count supported based on current mode. Signed-off-by: NWenjing Liu <wenjing.liu@amd.com> Reviewed-by: NAric Cyr <Aric.Cyr@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Wyatt Wood 提交于
[Why] When dmcub is the default we no longer wish to create the psr and dmcu objects. Currently a dc debug flag is used to implement this, but these flags aren't populated until after dcn21_resource_construct is called. This means the dmcub objects will never be created. Therefore we must use a dc config flag, which is populated before dc resource construct. [How] Add a dc config flag. Signed-off-by: NWyatt Wood <wyatt.wood@amd.com> Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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