1. 25 9月, 2019 22 次提交
  2. 21 9月, 2019 2 次提交
    • P
      MIPS: Detect bad _PFN_SHIFT values · 05d013a0
      Paul Burton 提交于
      2 recent commits have fixed issues where _PFN_SHIFT grew too large due
      to the introduction of too many pgprot bits in our PTEs for some MIPS32
      kernel configurations. Tracking down such issues can be tricky, so add a
      BUILD_BUG_ON() to help.
      Signed-off-by: NPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      05d013a0
    • P
      MIPS: Disable pte_special() for MIPS32 with RiXi · d1af2ab3
      Paul Burton 提交于
      Commit 61cbfff4 ("MIPS: pte_special()/pte_mkspecial() support")
      added a _PAGE_SPECIAL bit to the pgprot bits of our PTEs. Unfortunately
      for MIPS32 configurations with RiXi support this pushed the number of
      pgprot bits to 13. Since the PFN field in EntryLo begins at bit 12 this
      results in us shifting the most significant bit of the physical address
      beyond the end of the PTE, leading any mapped access to a physical
      address above 2GB to incorrectly access an address 2GB lower than
      intended.
      
      For now, disable the pte_special() support for MIPS32 configurations
      that support RiXi.
      
      Fixes: 61cbfff4 ("MIPS: pte_special()/pte_mkspecial() support")
      Signed-off-by: NPaul Burton <paul.burton@mips.com>
      Cc: Dmitry Korotin <dkorotin@wavecomp.com>
      Cc: linux-mips@vger.kernel.org
      d1af2ab3
  3. 19 9月, 2019 1 次提交
  4. 18 9月, 2019 3 次提交
  5. 17 9月, 2019 3 次提交
  6. 16 9月, 2019 9 次提交