- 08 12月, 2021 2 次提交
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由 Mike Tipton 提交于
Before commit fc0c209c ("clk: Allow parents to be specified without string names") child clks couldn't find their parent until the parent clk was added to a list in __clk_core_init(). After that commit, child clks can reference their parent clks directly via a clk_hw pointer, or they can lookup that clk_hw pointer via DT if the parent clk is registered with an OF clk provider. The common clk framework treats hw->core being non-NULL as "the clk is registered" per the logic within clk_core_fill_parent_index(): parent = entry->hw->core; /* * We have a direct reference but it isn't registered yet? * Orphan it and let clk_reparent() update the orphan status * when the parent is registered. */ if (!parent) Therefore we need to be extra careful to not set hw->core until the clk is fully registered with the clk framework. Otherwise we can get into a situation where a child finds a parent clk and we move the child clk off the orphan list when the parent isn't actually registered, wrecking our enable accounting and breaking critical clks. Consider the following scenario: CPU0 CPU1 ---- ---- struct clk_hw clkBad; struct clk_hw clkA; clkA.init.parent_hws = { &clkBad }; clk_hw_register(&clkA) clk_hw_register(&clkBad) ... __clk_register() hw->core = core ... __clk_register() __clk_core_init() clk_prepare_lock() __clk_init_parent() clk_core_get_parent_by_index() clk_core_fill_parent_index() if (entry->hw) { parent = entry->hw->core; At this point, 'parent' points to clkBad even though clkBad hasn't been fully registered yet. Ouch! A similar problem can happen if a clk controller registers orphan clks that are referenced in the DT node of another clk controller. Let's fix all this by only setting the hw->core pointer underneath the clk prepare lock in __clk_core_init(). This way we know that clk_core_fill_parent_index() can't see hw->core be non-NULL until the clk is fully registered. Fixes: fc0c209c ("clk: Allow parents to be specified without string names") Signed-off-by: NMike Tipton <quic_mdtipton@quicinc.com> Link: https://lore.kernel.org/r/20211109043438.4639-1-quic_mdtipton@quicinc.com [sboyd@kernel.org: Reword commit text, update comment] Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Dan Carpenter 提交于
This frees "name" and then tries to display in as part of the error message on the next line. Swap the order. Fixes: 1b2189f3 ("clk: versatile: clk-icst: Ensure clock names are unique") Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com> Link: https://lore.kernel.org/r/20211117072604.GC5237@kiliReviewed-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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- 07 12月, 2021 1 次提交
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由 Martin Botka 提交于
Without this change eMMC runs at overclocked freq. Swap the ops to not OC the eMMC. Signed-off-by: NMartin Botka <martin.botka@somainline.org> Link: https://lore.kernel.org/r/20211130212015.25232-1-martin.botka@somainline.orgReviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org> Fixes: 4b8d6ae5 ("clk: qcom: Add SM6125 (TRINKET) GCC driver") Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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- 03 12月, 2021 3 次提交
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由 Miles Chen 提交于
Replace builtin_platform_driver_probe with module_platform_driver_probe because CONFIG_CLK_IMX8QXP can be set to =m (kernel module). Fixes: e0d0d4d8 ("clk: imx8qxp: Support building i.MX8QXP clock driver as module") Cc: Fabio Estevam <festevam@gmail.com> Cc: Stephen Boyd <sboyd@kernel.org> Signed-off-by: NMiles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20210904235418.2442-1-miles.chen@mediatek.comReviewed-by: NFabio Estevam <festevam@gmail.com> Reviewed-by: NStephen Boyd <sboyd@kernel.org> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Bjorn Andersson 提交于
In the event that the bootloader has configured the Trion PLL as source for the display clocks, e.g. for the continuous splashscreen, then there will also be RCGs that are clocked by this instance. Reconfiguring, and in particular disabling the output of, the PLL will cause issues for these downstream RCGs and has been shown to prevent them from being re-parented. Follow downstream and skip configuration if it's determined that the PLL is already running. Fixes: 59128c20 ("clk: qcom: clk-alpha-pll: Add support for controlling Lucid PLLs") Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: NRobert Foss <robert.foss@linaro.org> Reviewed-by: NVinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20211123162508.153711-1-bjorn.andersson@linaro.orgSigned-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Dmitry Baryshkov 提交于
The function mux_get_parent() uses qcom_find_src_index() to find the parent clock index, which is incorrect: qcom_find_src_index() uses src enum for the lookup, while mux_get_parent() should use cfg field (which corresponds to the register value). Add qcom_find_cfg_index() function doing this kind of lookup and use it for mux parent lookup. Fixes: df964016 ("clk: qcom: add parent map for regmap mux") Cc: stable@vger.kernel.org Signed-off-by: NDmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20211115233407.1046179-1-dmitry.baryshkov@linaro.orgSigned-off-by: NStephen Boyd <sboyd@kernel.org>
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- 12 11月, 2021 2 次提交
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由 Rob Herring 提交于
Commit 2d3de197 ("ARM: dts: arm: Update ICST clock nodes 'reg' and node names") moved to using generic node names. That results in trying to register multiple clocks with the same name. Fix this by including the unit-address in the clock name. Fixes: 2d3de197 ("ARM: dts: arm: Update ICST clock nodes 'reg' and node names") Cc: stable@vger.kernel.org Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Stephen Boyd <sboyd@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-clk@vger.kernel.org Signed-off-by: NRob Herring <robh@kernel.org> Reviewed-by: NStephen Boyd <sboyd@kernel.org> Reviewed-by: NLinus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20211109164650.2233507-3-robh@kernel.org
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由 Paul Cercueil 提交于
Tidy up a bit the tree, by prefixing all include/dt-bindings/clock/ files related to Ingenic SoCs with 'ingenic,'. Signed-off-by: NPaul Cercueil <paul@crapouillou.net> Acked-by: NRob Herring <robh@kernel.org> Acked-by: NStephen Boyd <sboyd@kernel.org> Signed-off-by: NRob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211016133322.40771-1-paul@crapouillou.net
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- 06 11月, 2021 2 次提交
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由 Dmitry Baryshkov 提交于
The gcc_aggre1_pnoc_ahb_clk is crucial for the proper MSM8996/APQ8096 functioning. If it gets disabled, several subsytems will stop working (including eMMC/SDCC and USB). There are no in-kernel users of this clock, so it is much simpler to remove from the kernel. The clock was first removed in the commit 9e60de1c ("clk: qcom: Remove gcc_aggre1_pnoc_ahb_clk from msm8996") by Stephen Boyd, but got added back in the commit b5677521 ("clk: qcom: Add some missing gcc clks for msm8996") by Rajendra Nayak. Let's remove it again in hope that nobody adds it back. Reported-by: NVladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Cc: Rajendra Nayak <rnayak@codeaurora.org> Cc: Konrad Dybcio <konrad.dybcio@somainline.org> Fixes: b5677521 ("clk: qcom: Add some missing gcc clks for msm8996") Signed-off-by: NDmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20211104011155.2209654-1-dmitry.baryshkov@linaro.orgSigned-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Alexander Stein 提交于
Only imx8m_clk_hw_composite_core needs to set this flag. Fixes: a60fe746 ("clk: imx: Rework all imx_clk_hw_composite wrappers") Signed-off-by: NAlexander Stein <alexander.stein@ew.tq-group.com> Link: https://lore.kernel.org/r/20211103123947.3222443-1-alexander.stein@ew.tq-group.comReviewed-by: NAbel Vesa <abel.vesa@nxp.com> Tested-by: Adam Ford <aford173@gmail.com> #imx8mm-beacon Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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- 04 11月, 2021 2 次提交
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由 Joel Stanley 提交于
Move the soc revision parsing to the initial probe, saving the driver from parsing the register multiple times. Use this variable to select the correct divisor table for the AHB clock. Before this fix the A2 would have used the A0 table. Fixes: 2d491066 ("clk: ast2600: Fix AHB clock divider for A1") Signed-off-by: NJoel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210922235449.213631-1-joel@jms.id.auReviewed-by: NAndrew Jeffery <andrew@aj.id.au> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Alexander Stein 提交于
During commit 6594988f ("clk: composite: Use rate_ops.determine_rate when also a mux is available") setting req->best_parent_hw got lost, so best_parent_hw stays NULL during switch to the same parent. This results in the (debug) message: clk_calc_new_rates: lcdif_pixel not gated but wants to reparent and the following rate change is dropped. Fixes: 6594988f ("clk: composite: Use rate_ops.determine_rate when also a mux is available") Signed-off-by: NAlexander Stein <alexander.stein@ew.tq-group.com> Link: https://lore.kernel.org/r/20211103122441.3208576-1-alexander.stein@ew.tq-group.comReviewed-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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- 03 11月, 2021 10 次提交
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由 Heiko Stuebner 提交于
Both of these drivers were converted to real drivers and got a tristate build option. But them being builtin_platform_drivers, they only ever should be build-in - as the name suggests. So adapt the Kconfig symbol and drop the MODULE_* parts from the drivers. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20211027132616.1039814-3-heiko@sntech.deReviewed-by: NStephen Boyd <sboyd@kernel.org> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Heiko Stuebner 提交于
This reverts commit 1da80da0. Reading recent discussions [0] [1], I realized this change introduces a number of problems: - only converting to module_platform_driver creates the issue with the existing __init and __initdata attributes. When the driver would've been built as a module, all the missing clock-definitions (all are initdata) should've turned up as error in testing suggesting that the change wasn't at all - a clock driver is a very core component of soc bringup and making this able to be built as a module solely for enabling the soc vendor to add out of tree changes for Android implementations is not in our interest and also everything except a ramdisk won't probe without a clock controller. This is especially true when the changes aren't really tested and are merely added to move the mainline driver "out of the way". [0] https://lwn.net/Articles/872209/ [1] https://lore.kernel.org/all/163529604399.15791.378104318036812951@swboyd.mtv.corp.google.com/Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20211027132616.1039814-2-heiko@sntech.deReviewed-by: NStephen Boyd <sboyd@kernel.org> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Ran Jianping 提交于
'dt-bindings/clock/mt8195-clk.h' included in '/drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c' is duplicated.It is also included on the 13 line. Reported-by: NZeal Robot <zealci@zte.com.cn> Signed-off-by: NRan Jianping <ran.jianping@zte.com.cn> Link: https://lore.kernel.org/r/20211019062939.979660-1-ran.jianping@zte.com.cnReviewed-by: NChen-Yu Tsai <wenst@chromium.org> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Kunihiko Hayashi 提交于
Add SoC-glue clock source selector for ahci controller on UniPhier SoCs. Currently this supports Pro4 only. Signed-off-by: NKunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1634000035-3114-6-git-send-email-hayashi.kunihiko@socionext.comSigned-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Kunihiko Hayashi 提交于
Add basic clock data for UniPhier NX1 SoC. This includes PLL and clock division data for cpufreq support. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NKunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1634000035-3114-4-git-send-email-hayashi.kunihiko@socionext.comSigned-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Kunihiko Hayashi 提交于
Add clocks for audio subsystem (AIO) and video input subsystem (EXIV) on UniPhier PXs3 SoC. Signed-off-by: NKunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1634000035-3114-2-git-send-email-hayashi.kunihiko@socionext.comSigned-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Jens Renner 提交于
Silicon Labs is now part of Skyworks Inc. so update the URLs to the datasheet and application note. Signed-off-by: NJens Renner <renner@efe-gmbh.de> Link: https://lore.kernel.org/r/20210913074823.115212-1-renner@efe-gmbh.deAcked-by: NRob Herring <robh@kernel.org> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Luca Ceresoli 提交于
The old .probe is "soon to be deprecated". Use the new, simpler form. Signed-off-by: NLuca Ceresoli <luca@lucaceresoli.net> Link: https://lore.kernel.org/r/20210928095041.17116-1-luca@lucaceresoli.netSigned-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Mianhan Liu 提交于
owl-factor.c hasn't use any macro or function declared in linux/slab.h. Thus, these files can be removed from owl-factor.c safely without affecting the compilation of the ./drivers/clk module Signed-off-by: NMianhan Liu <liumh1@shanghaitech.edu.cn> Link: https://lore.kernel.org/r/20210929065824.23691-1-liumh1@shanghaitech.edu.cnReviewed-by: NManivannan Sadhasivam <mani@kernel.org> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Paul Cercueil 提交于
Two fixes in one: - In the "impose hardware constraints" block, the "logical" divider value (aka. not translated to the hardware) was clamped to fit in the register area, but this totally ignored the fact that the divider value can itself have a fixed divider. - The code that made sure that the divider value returned by the function was a multiple of its own fixed divider could result in a wrong value being calculated, because it was rounded down instead of rounded up. Fixes: 4afe2d1a ("clk: ingenic: Allow divider value to be divided") Co-developed-by: NArtur Rojek <contact@artur-rojek.eu> Signed-off-by: NArtur Rojek <contact@artur-rojek.eu> Signed-off-by: NPaul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20211001172033.122329-1-paul@crapouillou.netSigned-off-by: NStephen Boyd <sboyd@kernel.org>
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- 27 10月, 2021 16 次提交
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由 Claudiu Beznea 提交于
In case clock flags contains CLK_GET_RATE_NOCACHE the clk_rate_get() will return the cached rate. Thus, use clk_core_get_rate_recalc() which takes proper action when clock flags contains CLK_GET_RATE_NOCACHE. Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20211011112719.3951784-16-claudiu.beznea@microchip.comAcked-by: NNicolas Ferre <nicolas.ferre@microchip.com> [sboyd@kernel.org: Grab prepare lock around operation] Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Claudiu Beznea 提交于
MCK0 could go as low as 32KHz. Set this limit. Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20211011112719.3951784-15-claudiu.beznea@microchip.comAcked-by: NNicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Claudiu Beznea 提交于
On SAMA7G5 the prescaler part of master clock has been implemented as a changeable one. Everytime the prescaler is changed the PMC_SR.MCKRDY bit must be polled. Value 1 for PMC_SR.MCKRDY means the prescaler update is done. Driver polls for this bit until it becomes 1. On SAMA7G5 it has been discovered that in some conditions the PMC_SR.MCKRDY is not rising but the rate it provides it's stable. The workaround is to add a timeout when polling for PMC_SR.MCKRDY. At the moment, for SAMA7G5, the prescaler will be removed from Linux clock tree as all the frequencies for CPU could be obtained from PLL and also there will be less overhead when changing frequency via DVFS. Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20211011112719.3951784-14-claudiu.beznea@microchip.comAcked-by: NNicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Claudiu Beznea 提交于
SAMA7G5 supports DVFS by changing cpuck. On SAMA7G5 mck0 shares the same parent with cpuck as seen in the following clock tree: +----------> cpuck | FRAC PLL ---> DIV PLL -+-> DIV ---> mck0 mck0 could go b/w 32KHz and 200MHz on SAMA7G5. To avoid mck0 overclocking while changing FRAC PLL or DIV PLL the commit implements a notifier for mck0 which applies a safe divider to register (maximum value of the divider which is 5) on PRE_RATE_CHANGE events (such that changes on PLL to not overclock mck0) and sets the maximum allowed rate on POST_RATE_CHANGE events. Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20211011112719.3951784-13-claudiu.beznea@microchip.comAcked-by: NNicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Claudiu Beznea 提交于
SAM9X60's PLL which is also part of SAMA7G5 is composed of 2 parts: one fractional part and one divider. On SAMA7G5 the CPU PLL could be changed at run-time to implement DVFS. The hardware clock tree on SAMA7G5 for CPU PLL is as follows: +---- div1 ----------------> cpuck | FRAC PLL ---> DIV PLL -+-> prescaler ---> div0 ---> mck0 The div1 block is not implemented in Linux; on prescaler block it has been discovered a bug on some scenarios and will be removed from Linux in next commits. Thus, the final clock tree that will be used in Linux will be as follows: +-----------> cpuck | FRAC PLL ---> DIV PLL -+-> div0 ---> mck0 It has been proposed in [1] to not introduce a new CPUFreq driver but to overload the proper clock drivers with proper operation such that cpufreq-dt to be used. To accomplish this DIV PLL and div0 implement clock notifiers which applies safe dividers before FRAC PLL is changed. The current commit treats only the DIV PLL by adding a notifier that sets a safe divider on PRE_RATE_CHANGE events. The safe divider is provided by initialization clock code (sama7g5.c). The div0 is treated in next commits (to keep the changes as clean as possible). [1] https://lore.kernel.org/lkml/20210105104426.4tmgc2l3vyicwedd@vireshk-i7/Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20211011112719.3951784-12-claudiu.beznea@microchip.comAcked-by: NNicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Claudiu Beznea 提交于
When prescaler value read from register is MASTER_PRES_MAX it means that the input clock will be divided by 3. Fix the code to reflect this. Fixes: 7a110b91 ("clk: at91: clk-master: re-factor master clock") Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20211011112719.3951784-11-claudiu.beznea@microchip.comAcked-by: NNicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Claudiu Beznea 提交于
Mask values read/written from/to MCKR against layout->mask as this mask may be different b/w PMC versions. Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20211011112719.3951784-10-claudiu.beznea@microchip.comAcked-by: NNicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Claudiu Beznea 提交于
Check if div or pres is zero before using it as argument for ffs(). In case div is zero ffs() will return 0 and thus substracting from zero will lead to invalid values to be setup in registers. Fixes: 7a110b91 ("clk: at91: clk-master: re-factor master clock") Fixes: 75c88143 ("clk: at91: clk-master: add master clock support for SAMA7G5") Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20211011112719.3951784-9-claudiu.beznea@microchip.comAcked-by: NNicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Claudiu Beznea 提交于
Use DIV_ROUND_CLOSEST_ULL() to avoid any inconsistency b/w the rate computed in sam9x60_frac_pll_recalc_rate() and the one computed in sam9x60_frac_pll_compute_mul_frac(). Fixes: 43b1bb4a ("clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputs") Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20211011112719.3951784-8-claudiu.beznea@microchip.comAcked-by: NNicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Claudiu Beznea 提交于
Add SAMA7G5 to the list of available PMCs such that the suspend/resume code for clocks to be used on backup mode. Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20211011112719.3951784-7-claudiu.beznea@microchip.comAcked-by: NNicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Claudiu Beznea 提交于
Improve readability in clk_sama7g5_master_set() by using local variables. Suggested-by: NNicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20211011112719.3951784-6-claudiu.beznea@microchip.comAcked-by: NNicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Claudiu Beznea 提交于
SAMA7G5 has 4 master clocks (MCK1..4) which are controlled though the register at offset 0x30 (relative to PMC). In the last/first phase of suspend/resume procedure (which is architecture specific) the parent of master clocks are changed (via assembly code) for more power saving (see file arch/arm/mach-at91/pm_suspend.S, macros at91_mckx_ps_enable and at91_mckx_ps_restore). Thus the macros corresponding to register at offset 0x30 need to be shared b/w clk-master.c and pm_suspend.S. commit ec03f18c ("clk: at91: add register definition for sama7g5's master clock") introduced the proper macros but didn't adapted the clk-master.c as well. Thus, this commit adapt the clk-master.c to use the macros introduced in commit ec03f18c ("clk: at91: add register definition for sama7g5's master clock"). Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20211011112719.3951784-5-claudiu.beznea@microchip.comAcked-by: NNicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Claudiu Beznea 提交于
Add SECURAM's peripheral clock. Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Acked-by: NNicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20211011112719.3951784-4-claudiu.beznea@microchip.comSigned-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Claudiu Beznea 提交于
Before going to backup mode architecture specific PM code sets the first word in securam (file arch/arm/mach-at91/pm.c, function at91_pm_begin()). Thus take this into account when suspending/resuming clocks. This will avoid executing unnecessary instructions when suspending to non backup modes. Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20211011112719.3951784-3-claudiu.beznea@microchip.comAcked-by: NNicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Claudiu Beznea 提交于
SAMA5D2 and SAMA7G5 have a special power saving mode (backup mode) where most of the SoC's components are powered off (including PMC). Resuming from this mode is done with the help of bootloader. Peripherals are not aware of the power saving mode thus most of them are disabling clocks in proper suspend API and re-enable them in resume API without taking into account the previously setup rate. Moreover some of the peripherals are acting as wakeup sources and are not disabling the clocks in this scenario, when suspending. Since backup mode cuts the power for peripherals, in resume part these clocks needs to be re-configured. The initial PMC suspend/resume code was designed only for SAMA5D2's PMC (as it was the only one supporting backup mode). SAMA7G supports also backup mode and its PMC is different (few new functionalities, different registers offsets, different offsets in registers for each functionalities). To address both SAMA5D2 and SAMA7G5 PMC add .save_context()/.resume_context() support to each clocks driver and call this from PMC driver. Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20211011112719.3951784-2-claudiu.beznea@microchip.comAcked-by: NNicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Linus Walleij 提交于
The Ux500 PRCC (peripheral reset and clock controller) can also control reset of the IP blocks, not just clocks. As the PRCC is probed as a clock controller and we have other platforms implementing combined clock and reset controllers, follow this pattern and implement the PRCC rest controller as part of the clock driver. The reset controller needs to be selected from the machine as Ux500 has traditionally selected its mandatory subsystem prerequisites from there. Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20210921184803.1757916-2-linus.walleij@linaro.orgAcked-by: NUlf Hansson <ulf.hansson@linaro.org> [sboyd@kernel.org: Dropped allocation error message] Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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- 21 10月, 2021 1 次提交
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由 Miquel Raynal 提交于
Declare ADC1 clkctrl which feeds the magnetic-reader/ADC1 hardware module. Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com> Acked-by: NStephen Boyd <sboyd@kernel.org> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NLee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20211015081506.933180-2-miquel.raynal@bootlin.com
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- 19 10月, 2021 1 次提交
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由 Martin Blumenstingl 提交于
Update clk_composite_determine_rate() to use rate_ops.determine_rate when available in combination with a mux. So far clk_divider_ops provide both, .round_rate and .determine_rate. Removing the former would make clk-composite fail silently for example on Rockchip platforms (which heavily use composite clocks). Add support for using rate_ops.determine_rate when either rate_ops.round_rate is not available or both (.round_rate and .determine_rate) are provided. Suggested-by: NAlex Bee <knaerzche@gmail.com> Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20211016105022.303413-3-martin.blumenstingl@googlemail.comTested-by: NAlex Bee <knaerzche@gmail.com> Tested-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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