- 05 2月, 2015 1 次提交
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由 Geert Uytterhoeven 提交于
Anyone may call clk_round_rate() with a zero rate value, so we have to protect against that. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Acked-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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- 04 2月, 2015 2 次提交
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由 Stefan Wahren 提交于
According to i.MX23 and i.MX28 reference manual [1],[2] the fractional clock control register is 32-bit wide, but is separated in 4 parts. So write instructions must not apply to more than 1 part at once. The clk init for the i.MX28 violates this restriction and all the other accesses on that register suggest that there isn't such a restriction. This patch restricts the access to this register to byte instructions and extends the comment in the init functions. Btw the imx23 init now uses a R-M-W sequence just like imx28 init to avoid any clock glitches. The changes has been tested with a i.MX23 and a i.MX28 board. [1] - http://cache.freescale.com/files/dsp/doc/ref_manual/IMX23RM.pdf [2] - http://cache.freescale.com/files/dsp/doc/ref_manual/MCIMX28RM.pdfSigned-off-by: NStefan Wahren <stefan.wahren@i2se.com> Reviewed-by: NMarek Vasut <marex@denx.de> Reviewed-by: NFabio Estevam <fabio.estevam@freescale.com> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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由 Arnd Bergmann 提交于
The 'ARM: OMAP3: legacy clock data move under clk driver' patch series causes build errors when CONFIG_OMAP3 is not set: drivers/clk/ti/dpll.c: In function 'ti_clk_register_dpll': drivers/clk/ti/dpll.c:199:31: error: 'omap3_dpll_ck_ops' undeclared (first use in this function) const struct clk_ops *ops = &omap3_dpll_ck_ops; ^ drivers/clk/ti/dpll.c:199:31: note: each undeclared identifier is reported only once for each function it appears in drivers/clk/ti/dpll.c:259:10: error: 'omap3_dpll_per_ck_ops' undeclared (first use in this function) ops = &omap3_dpll_per_ck_ops; ^ drivers/built-in.o: In function `ti_clk_register_gate': drivers/clk/ti/gate.c:179: undefined reference to `clkhwops_omap3430es2_dss_usbhost_wait' drivers/clk/ti/gate.c:179: undefined reference to `clkhwops_am35xx_ipss_module_wait' -in.o: In function `ti_clk_register_interface': drivers/clk/ti/interface.c:100: undefined reference to `clkhwops_omap3430es2_iclk_hsotgusb_wait' drivers/clk/ti/interface.c:100: undefined reference to `clkhwops_omap3430es2_iclk_dss_usbhost_wait' drivers/clk/ti/interface.c:100: undefined reference to `clkhwops_omap3430es2_iclk_ssi_wait' drivers/clk/ti/interface.c:100: undefined reference to `clkhwops_am35xx_ipss_wait' drivers/built-in.o: In function `ti_clk_register_composite': :(.text+0x3da768): undefined reference to `ti_clk_build_component_gate' In order to fix that problem, this patch makes the omap3 legacy code compiled only when both CONFIG_OMAP3 and CONFIG_ATAGS are set. Signed-off-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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- 03 2月, 2015 4 次提交
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由 Tomeu Vizoso 提交于
So it can be used from modules such as clk-test.ko. Signed-off-by: NTomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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由 Tomeu Vizoso 提交于
Adds a way for clock consumers to set maximum and minimum rates. This can be used for thermal drivers to set minimum rates, or by misc. drivers to set maximum rates to assure a minimum performance level. Changes the signature of the determine_rate callback by adding the parameters min_rate and max_rate. Signed-off-by: NTomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org> [sboyd@codeaurora.org: set req_rate in __clk_init] Signed-off-by: NMichael Turquette <mturquette@linaro.org> [mturquette@linaro.org: min/max rate for sun6i_ahb1_clk_determine_rate migrated clk-private.h changes to clk.c]
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由 Michael Turquette 提交于
Private clock framework data structures should be private, surprisingly. Now that all platforms and drivers have been updated to remove static initializations of struct clk and struct clk_core objects and all references to clk-private.h have been removed we can move the definitions of these structures into drivers/clk/clk.c and delete the header. Additionally the ugly DEFINE_CLK macros have been removed. Those were used for static definitions of struct clk objects. That practice is no longer allowed. Finally __clk_init is staticized as it is no longer declared in any header. Reviewed-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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由 Tomeu Vizoso 提交于
Moves clock state to struct clk_core, but takes care to change as little API as possible. struct clk_hw still has a pointer to a struct clk, which is the implementation's per-user clk instance, for backwards compatibility. The struct clk that clk_get_parent() returns isn't owned by the caller, but by the clock implementation, so the former shouldn't call clk_put() on it. Because some boards in mach-omap2 still register clocks statically, their clock registration had to be updated to take into account that the clock information is stored in struct clk_core now. Signed-off-by: NTomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by: NStephen Boyd <sboyd@codeaurora.org> Tested-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NMichael Turquette <mturquette@linaro.org> [mturquette@linaro.org: adapted clk_has_parent to struct clk_core applied OMAP3+ DPLL fix from Tero & Tony]
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- 02 2月, 2015 6 次提交
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由 Mark Zhang 提交于
PLLD is the only parent for DSIA & DSIB on Tegra124 and Tegra132. Besides, BIT 30 in PLLD_MISC register controls the output of DSI clock. So this patch removes "dsia_mux" & "dsib_mux", and create a new clock "plld_dsi" to represent the DSI clock enable control. Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: NMark Zhang <markz@nvidia.com>
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由 Paul Walmsley 提交于
Tegra132 CAR supports almost the same clocks as Tegra124 CAR. This patch mostly deals with the small differences. Since Tegra132 contains many of the same PLL clock sources used on Tegra114 and Tegra124, enable them in drivers/clk/tegra/clk-pll.c when the kernel is configured to include Tegra132 support. This patch is based on several patches from others: 1. a patch from Peter De Schrijver: http://lkml.iu.edu/hypermail/linux/kernel/1407.1/06094.html 2. a patch from Bill Huang ("clk: tegra: enable cclk_g at boot on Tegra132"), and 3. a patch from Allen Martin ("clk: Enable tegra clock driver for tegra132"). Signed-off-by: NPaul Walmsley <paul@pwsan.com> Signed-off-by: NPaul Walmsley <pwalmsley@nvidia.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Allen Martin <amartin@nvidia.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: Bill Huang <bilhuang@nvidia.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Stephen Boyd <sboyd@codeaurora.org>
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由 Peter De Schrijver 提交于
tegra_clocks_apply_init_table() needs to be called after the udelay loop has been calibrated (see commit 441f199a ("clk: tegra: defer application of init table") for why that is). On existing Tegra SoCs this was done by calling tegra_clocks_apply_init_table() from tegra_dt_init(). To make this also work on ARM64, we need to change this into an initcall. tegra_dt_init() is called from customize_machine which is an arch_initcall. Therefore this should also work on existing 32bit Tegra SoCs. Tested on Tegra20 (ventana), Tegra30 (beaverboard), Tegra124 (jetson TK1) and Tegra132. Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com> [paul@pwsan.com: tweaked the commit message] Signed-off-by: NPaul Walmsley <paul@pwsan.com> Signed-off-by: NPaul Walmsley <pwalmsley@nvidia.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Alexandre Courbot <gnurou@gmail.com>
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由 Tomeu Vizoso 提交于
As previously the names of the present clock and its parent were swapped. Signed-off-by: NTomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
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由 Sean Paul 提交于
Set the parent of the dsi lp clocks to pll_p and the rate to 68MHz. The default parent is clk_m and rate is 12MHz, this is too slow to receive data from the peripheral. Per NVidia HW engineers, the optimal rate is 70MHz, but 68MHz will suffice. Signed-off-by: NSean Paul <seanpaul@chromium.org> Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
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由 Andrew Bresticker 提交于
Since the SDMMC controller registers are accessed via the APB, the APB must be flushed before gating the SDMMC clocks to prevent register accesses to the SDMMC controllers after their clocks are gated. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
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- 31 1月, 2015 8 次提交
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由 Tero Kristo 提交于
Introduces omap3 legacy clock data under clock driver. The clock data is also in new format, which makes it possible to get rid of the clk-private.h header. This patch also introduces SoC specific init functions that shall be called from the low level init. The data format used in this file has two possible evolution paths; it can either be removed completely once no longer needed, or it will be possible to retain the format and modify the TI clock driver to be a loadable module at some point. The actual path to be followed will be decided later. Signed-off-by: NTero Kristo <t-kristo@ti.com> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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由 Tero Kristo 提交于
Legacy clock data is initialized slightly differently compared to DT clocks, thus add support for this. Signed-off-by: NTero Kristo <t-kristo@ti.com> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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由 Tero Kristo 提交于
Legacy clock data is initialized slightly differently compared to DT clocks, thus add support for this. Signed-off-by: NTero Kristo <t-kristo@ti.com> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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由 Tero Kristo 提交于
Legacy clock data is initialized slightly differently compared to DT clocks, thus add support for this. Signed-off-by: NTero Kristo <t-kristo@ti.com> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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由 Tero Kristo 提交于
Legacy clock data is initialized slightly differently compared to DT clocks, thus add support for this. The interface clock descriptor itself is overloading the gate clock descriptor, thus it needs to be called from the gate setup. Signed-off-by: NTero Kristo <t-kristo@ti.com> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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由 Tero Kristo 提交于
Legacy clock data is initialialized slightly differently compared to DT clocks, thus add support for this. Signed-off-by: NTero Kristo <t-kristo@ti.com> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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由 Tero Kristo 提交于
Legacy clock data is initialized slightly differently compared to DT clocks, thus add support for this. Signed-off-by: NTero Kristo <t-kristo@ti.com> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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由 Tero Kristo 提交于
Legacy clock data for OMAP3 is being moved under clock driver, thus base support for this is needed. This patch adds basic definitions for clock init descriptors and core infrastructure for initialization, which will be called from the OMAP3 clock init. Signed-off-by: NTero Kristo <t-kristo@ti.com> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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- 29 1月, 2015 9 次提交
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由 Tomeu Vizoso 提交于
As it has never been used. Signed-off-by: NTomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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由 Tomeu Vizoso 提交于
As clk_unprepare_unused_subtree and clk_disable_unused_subtree are always called with a valid struct clk. Signed-off-by: NTomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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由 Emil Medve 提交于
Currently a mix of clk-qoriq/qoriq-clk and no prefix is used Signed-off-by: NEmil Medve <Emilian.Medve@Freescale.com> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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由 Emil Medve 提交于
Where the memset() is not necessary Signed-off-by: NEmil Medve <Emilian.Medve@Freescale.com> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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由 Emil Medve 提交于
drivers/clk/clk-qoriq.c:59:22: warning: symbol 'cmux_ops' was not declared. Should it be static? Signed-off-by: NEmil Medve <Emilian.Medve@Freescale.com> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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由 Emil Medve 提交于
WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message + if (!parent_names) { + pr_err("%s: could not allocate parent_names\n", __func__); WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message + if (!cmux_clk) { + pr_err("%s: could not allocate cmux_clk\n", __func__); WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message + if (!subclks) { + pr_err("%s: could not allocate subclks\n", __func__); WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message + if (!onecell_data) { + pr_err("%s: could not allocate onecell_data\n", __func__); Signed-off-by: NEmil Medve <Emilian.Medve@Freescale.com> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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由 Emil Medve 提交于
CHECK:ALLOC_SIZEOF_STRUCT: Prefer kzalloc(sizeof(*cmux_clk)...) over kzalloc(sizeof(struct cmux_clk)...) + cmux_clk = kzalloc(sizeof(struct cmux_clk), GFP_KERNEL); CHECK:ALLOC_SIZEOF_STRUCT: Prefer kzalloc(sizeof(*onecell_data)...) over kzalloc(sizeof(struct clk_onecell_data)...) + onecell_data = kzalloc(sizeof(struct clk_onecell_data), GFP_KERNEL); Signed-off-by: NEmil Medve <Emilian.Medve@Freescale.com> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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由 Emil Medve 提交于
WARNING:ALLOC_WITH_MULTIPLY: Prefer kcalloc over kzalloc with multiply + subclks = kzalloc(sizeof(struct clk *) * count, GFP_KERNEL); Signed-off-by: NEmil Medve <Emilian.Medve@Freescale.com> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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由 Emil Medve 提交于
CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis + rc = of_property_read_string_index(np, "clock-output-names", + 0, &clk_name); CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis + pr_err("Could not register clock provider for node:%s\n", + np->name); CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis + rc = of_property_read_string_index(np, "clock-output-names", + i, &clk_name); CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis + pr_err("Could not register clk provider for node:%s\n", + np->name); Signed-off-by: NEmil Medve <Emilian.Medve@Freescale.com> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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- 28 1月, 2015 10 次提交
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由 Chanwoo Choi 提交于
This patch adds the divider clock id for Exynos4 memory bus frequency. The clock id is used for DVFS (Dynamic Voltage/Frequency Scaling) feature of the exynos memory bus. Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com> Acked-by: NMyungJoo Ham <myungjoo.ham@samsung.com> Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
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由 Robert Jarzmik 提交于
Move pxa25x clock drivers from arch/arm/mach-pxa to driver/clk. In the move : - convert to new clock framework legacy clocks - provide clocks as before for platform data based boards - provide clocks through devicetree with clk-pxa-dt Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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由 Soren Brinkmann 提交于
The CPU_2X clock does not have a classical in-kernel user, but is, amongst other things, required for OCM and debug access. Make sure this clock is not mistakenly disabled during boot up by enabling it in the platform's clock driver. Cc: stable@vger.kernel.org # 3.11+ Fixes: 0ee52b15 'clk: zynq: Add clock controller driver' Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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由 Stephen Boyd 提交于
These modules don't need to include clk-private.h. Replace the include with clk.h because these modules are clock consumers and also include clk-provider.h in clk/ti.h because struct clk_hw_omap has a struct clk_hw embedded in it. Cc: Tero Kristo <t-kristo@ti.com> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org> Reviewed-by: NPaul Walmsley <paul@pwsan.com> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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由 Stephen Boyd 提交于
These drivers don't need to include clk-private.h. Remove the include. Signed-off-by: NStephen Boyd <sboyd@codeaurora.org> Acked-by: NUlf Hansson <ulf.hansson@linaro.org> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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由 Maxime Ripard 提交于
The phase setter and getter were not exported until now, which was causing build breakages when callers were compiled as module. Export these two functions. Reported-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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由 Stephen Boyd 提交于
Add an LCC driver for MSM8960/APQ8064 that supports the i2s, slimbus, and pcm clocks. Signed-off-by: NStephen Boyd <sboyd@codeaurora.org> Tested-by: NKenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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由 Rajendra Nayak 提交于
Add an LCC driver for IPQ806x that supports the i2s, S/PDIF, and pcm clocks. Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org> Signed-off-by: NKumar Gala <galak@codeaurora.org> Signed-off-by: NJosh Cartwright <joshc@codeaurora.org> [sboyd@codeaurora.org: Reworded commit text, added Kconfig select, fleshed out Kconfig description a bit more, added pll4 configuration and reworked probe for it, added muxes, split out dt-binding file] Signed-off-by: NStephen Boyd <sboyd@codeaurora.org> Tested-by: NKenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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由 Stephen Boyd 提交于
Add support for muxes that use regmap instead of readl/writel directly. We don't support as many features as clk-mux.c, but this is good enough to support getting and setting parents. Adding a table based lookup can be added in the future if needed. Signed-off-by: NStephen Boyd <sboyd@codeaurora.org> Tested-by: NKenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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由 Josh Cartwright 提交于
Add support for dividers that use regmap instead of readl/writel. Signed-off-by: NJosh Cartwright <joshc@codeaurora.org> Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org> [sboyd@codeaurora.org: Switch to using generic divider code, drop enable/disable, reword commit text] Signed-off-by: NStephen Boyd <sboyd@codeaurora.org> Tested-by: NKenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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