Some interrupt controllers have inverted status register:
cleared bits is active interrupts and set bits is inactive interrupts,
so add inverted status support to the framework.
Signed-off-by: NMaxim Kochetkov <fido_max@inbox.ru>
Link: https://lore.kernel.org/r/20210525034204.5272-1-fido_max@inbox.ruSigned-off-by: NMark Brown <broonie@kernel.org>

Basic support for MDIO bus access. Support only includes clause-22
register access, with 5-bit addresses, and 16-bit wide registers.
Signed-off-by: NSander Vanheule <sander@svanheule.net>
Link: https://lore.kernel.org/r/63b99a2fec2c4ea3c461d59d451af8d675ecf312.1621279162.git.sander@svanheule.netSigned-off-by: NMark Brown <broonie@kernel.org>

Set regmap raw read/write from i2c quirks max read/write
so regmap_raw_read/write can split the access into chunks
Signed-off-by: NLucas Tanure <tanureal@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20210512135222.223203-1-tanureal@opensource.cirrus.comSigned-off-by: NMark Brown <broonie@kernel.org>

Enable drivers to configure and modify "virtual" registers, which are
non-standard registers that further configure irq type on some devices.
Since they are non-standard, enable drivers to configure them according
to their particular idiosyncrasies by specifying an optional callback
function while registering with the framework.
Signed-off-by: NGuru Das Srinagesh <gurus@codeaurora.org>
Link: https://lore.kernel.org/r/07e058cdec2297d15c95c825aa0263064d962d5a.1616613838.git.gurus@codeaurora.orgSigned-off-by: NMark Brown <broonie@kernel.org>

Add "virtual" registers support to handle any irq configuration
registers in addition to the ones the framework currently supports
(status, mask, unmask, wake, type and ack). These are non-standard
registers that further configure irq type on some devices, so enable the
framework to add a variable number of them.
Signed-off-by: NGuru Das Srinagesh <gurus@codeaurora.org>
Link: https://lore.kernel.org/r/a1787067004b0e11cb960319082764397469215a.1616613838.git.gurus@codeaurora.orgSigned-off-by: NMark Brown <broonie@kernel.org>

Qualcomm's MFD chips have a top level interrupt status register and
sub-irqs (peripherals).  When a bit in the main status register goes
high, it means that the peripheral corresponding to that bit has an
unserviced interrupt. If the bit is not set, this means that the
corresponding peripheral does not.

Commit a2d21848 ("regmap: regmap-irq: Add main status register
support") introduced the sub-irq logic that is currently applied only
when reading status registers, but not for any other functions like acking
or masking. Extend the use of sub-irq to all other functions, with two
caveats regarding the specification of offsets:

- Each member of the sub_reg_offsets array should be of length 1
- The specified offsets should be the unequal strides for each sub-irq
  device.

In QCOM's case, all the *_base registers are to be configured to the
base addresses of the first sub-irq group, with offsets of each
subsequent group calculated as a difference from these addresses.

Continuing from the example mentioned in the cover letter:

	/*
	 * Address of MISC_INT_MASK		= 0x1011
	 * Address of TEMP_ALARM_INT_MASK	= 0x2011
	 * Address of GPIO01_INT_MASK		= 0x3011
	 *
	 * Calculate offsets as:
	 * offset_0 = 0x1011 - 0x1011 = 0       (to access MISC's
	 * 					 registers)
	 * offset_1 = 0x2011 - 0x1011 = 0x1000
	 * offset_2 = 0x3011 - 0x1011 = 0x2000
	 */

	static unsigned int sub_unit0_offsets[] = {0};
	static unsigned int sub_unit1_offsets[] = {0x1000};
	static unsigned int sub_unit2_offsets[] = {0x2000};

	static struct regmap_irq_sub_irq_map chip_sub_irq_offsets[] = {
		REGMAP_IRQ_MAIN_REG_OFFSET(sub_unit0_offsets),
		REGMAP_IRQ_MAIN_REG_OFFSET(sub_unit0_offsets),
		REGMAP_IRQ_MAIN_REG_OFFSET(sub_unit0_offsets),
	};

	static struct regmap_irq_chip chip_irq_chip = {
	--------8<--------
	.not_fixed_stride = true,
	.mask_base	  = MISC_INT_MASK,
	.type_base	  = MISC_INT_TYPE,
	.ack_base	  = MISC_INT_ACK,
	.sub_reg_offsets  = chip_sub_irq_offsets,
	--------8<--------
	};
Signed-off-by: NGuru Das Srinagesh <gurus@codeaurora.org>
Link: https://lore.kernel.org/r/526562423eaa58b4075362083f561841f1d6956c.1615423027.git.gurus@codeaurora.orgSigned-off-by: NMark Brown <broonie@kernel.org>

The SoundWire 1.1 specification only allowed for reads and writes of
bytes. The SoundWire 1.2 specification adds a new capability to
transfer "Multi-Byte Quantities" (MBQ) across the bus. The transfers
still happens one-byte-at-a-time, but the update is atomic.

For example when writing a 16-bit volume, the first byte transferred
is only taken into account when the second byte is successfully
transferred.

The mechanism is symmetrical for read and writes:
- On a read, the address of the last byte to be read is modified by
setting the MBQ bit
- On a write, the address of all but the last byte to be written are
modified by setting the MBQ bit. The address for the last byte relies
on the MBQ bit being cleared.

The current definitions for MBQ-based controls in the SDCA draft
standard are limited to 16 bits for volumes, so for now this is the
only supported format. An update will be provided if and when support
for 24-bit and 32-bit values is specified by the SDCA standard.

One possible objection is that this code could have been handled with
regmap-sdw.c. However this is a new spec addition not handled by every
SoundWire 1.1 and non-SDCA device, so there's no reason to load code
that will never be used.

Also in practice it's extremely unlikely that CONFIG_REGMAP would not
be selected with CONFIG_REGMAP_MBQ selected. However there's no
functional dependency between the two modules so they can be selected
separately.
Reviewed-by: NRander Wang <rander.wang@linux.intel.com>
Reviewed-by: NGuennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Reviewed-by: NKai Vehmanen <kai.vehmanen@linux.intel.com>
Signed-off-by: NPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: NBard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: NVinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20201103172226.4278-3-yung-chuan.liao@linux.intel.comSigned-off-by: NMark Brown <broonie@kernel.org>

On some platforms (eg armv7 due to the CONFIG_ARM_DMA_MEM_BUFFERABLE)
MMIO R/W operations always add memory barriers which can increase load,
decrease battery life or in general reduce performance unnecessarily
on devices which access a lot of configuration registers and where
ordering does not matter (eg. media accelerators like the Verisilicon /
Hantro video decoders).

Drivers used to call the relaxed MMIO variants directly but since they
are now accessing the MMIO registers via regmaps (to compensate for
different VPU HW reg layouts via regmap fields), there is a need for a
relaxed API / config to preserve existing behaviour.

Cc: Mark Brown <broonie@kernel.org>
Signed-off-by: NAdrian Ratiu <adrian.ratiu@collabora.com>
Link: https://lore.kernel.org/r/20201014203024.954369-1-adrian.ratiu@collabora.comSigned-off-by: NMark Brown <broonie@kernel.org>

For particular codec HWs have requirement to toggle interrupt clear
register twice 0->1->0. To accommodate it, need to add one more field
(clear_ack) in the regmap_irq struct and update regmap-irq driver to
support it.
Signed-off-by: NLaxminath Kasam <lkasam@codeaurora.org>
Link: https://lore.kernel.org/r/1601907440-13373-1-git-send-email-lkasam@codeaurora.orgSigned-off-by: NMark Brown <broonie@kernel.org>

Usage of regmap_field_alloc becomes much overhead when number of fields
exceed more than 3.
QCOM LPASS driver has extensively converted to use regmap_fields.

Using new bulk api to allocate fields makes it much more cleaner code to read!
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Tested-by: NSrinivasa Rao Mandadapu <srivasam@codeaurora.org>
Link: https://lore.kernel.org/r/20200925164856.10315-2-srinivas.kandagatla@linaro.orgSigned-off-by: NMark Brown <broonie@kernel.org>

Regmap can't sleep if spinlock is used for the locking protection.
This patch fixes regression caused by a previous commit that switched
regmap to use fsleep() and this broke Amlogic S922X platform.

This patch adds new configuration option for regmap users, allowing to
specify whether regmap operations can sleep and assuming that sleep is
allowed if mutex is used for the regmap locking protection.
Reported-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Fixes: 2b32d2f7 ("regmap: Use flexible sleep")
Signed-off-by: NDmitry Osipenko <digetx@gmail.com>
Tested-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Link: https://lore.kernel.org/r/20200902141843.6591-1-digetx@gmail.comSigned-off-by: NMark Brown <broonie@kernel.org>

This patch add support for regmap APIs that are intended to be used by
the drivers of some SPI slave chips which integrate the "SPI slave to
Avalon Master Bridge" (spi-avmm) IP.

The spi-avmm IP acts as a bridge to convert encoded streams of bytes
from the host to the chip's internal register read/write on Avalon bus.
The driver implements the register read/write operations for a generic
SPI master to access the sub devices behind spi-avmm bridge.
Signed-off-by: NXu Yilun <yilun.xu@intel.com>
Signed-off-by: NWu Hao <hao.wu@intel.com>
Signed-off-by: NMatthew Gerlach <matthew.gerlach@linux.intel.com>
Signed-off-by: NRuss Weight <russell.h.weight@intel.com>
Reviewed-by: NTom Rix <trix@redhat.com>
Reviewed-by: NLuis Claudio R. Goncalves <lgoncalv@redhat.com>
Link: https://lore.kernel.org/r/1597822497-25107-2-git-send-email-yilun.xu@intel.comSigned-off-by: NMark Brown <broonie@kernel.org>

Change doubled word "be" to "to be".
Signed-off-by: NRandy Dunlap <rdunlap@infradead.org>
Cc: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/7ef41bfc-de3e-073a-8746-0b3fdf7628c0@infradead.orgSigned-off-by: NMark Brown <broonie@kernel.org>

Convert the argument to the newer fwnode_handle instead a device tree
node. Fortunately, there are no users for now. So this is an easy
change.
Signed-off-by: NMichael Walle <michael@walle.cc>
Link: https://lore.kernel.org/r/20200706175353.16404-2-michael@walle.ccSigned-off-by: NMark Brown <broonie@kernel.org>

There's no reason to have these as macros. Let's convert them all to
static inlines for better readability and stronger typing.
Suggested-by: NMark Brown <broonie@kernel.org>
Signed-off-by: NBartosz Golaszewski <bgolaszewski@baylibre.com>
Link: https://lore.kernel.org/r/20200615072313.11106-1-brgl@bgdev.plSigned-off-by: NMark Brown <broonie@kernel.org>

In many instances regmap_update_bits() is used for simple bit setting
and clearing. In these cases the last argument is redundant and we can
hide it with a static inline function.

This adds three new helpers for simple bit operations: set_bits,
clear_bits and test_bits (the last one defined as a regular function).
Signed-off-by: NBartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

In many instances regmap_update_bits() is used for simple bit setting
and clearing. In these cases the last argument is redundant and we can
hide it with a static inline function.

This adds three new helpers for simple bit operations: set_bits,
clear_bits and test_bits (the last one defined as a regular function).
Signed-off-by: NBartosz Golaszewski <bgolaszewski@baylibre.com>
Link: https://lore.kernel.org/r/20200528154503.26304-2-brgl@bgdev.plSigned-off-by: NMark Brown <broonie@kernel.org>

Similar to the standalone regfields, add an initializer for the users
who need to set .id_size and .id_offset in order to use the
regmap_fields_update_bits_base API.
Signed-off-by: NVladimir Oltean <vladimir.oltean@nxp.com>
Link: https://lore.kernel.org/r/20200527234113.2491988-2-olteanv@gmail.comSigned-off-by: NMark Brown <broonie@kernel.org>

Simplify the implementation of the macro regmap_field_read_poll_timeout()
by using the macro read_poll_timeout().
Signed-off-by: NDejin Zheng <zhengdejin5@gmail.com>
Link: https://lore.kernel.org/r/20200420134647.9121-3-zhengdejin5@gmail.comSigned-off-by: NMark Brown <broonie@kernel.org>

Simplify the implementation of the macro regmap_read_poll_timeout()
by using the macro read_poll_timeout().
Signed-off-by: NDejin Zheng <zhengdejin5@gmail.com>
Link: https://lore.kernel.org/r/20200420134647.9121-2-zhengdejin5@gmail.comSigned-off-by: NMark Brown <broonie@kernel.org>

Add helper to make it easier to define a reg_sequence array.
Signed-off-by: NMarco Felsch <m.felsch@pengutronix.de>
Link: https://lore.kernel.org/r/20200402084111.30123-1-m.felsch@pengutronix.deSigned-off-by: NMark Brown <broonie@kernel.org>

Add a new function regmap_add_irq_chip_np() with its corresponding
devm_regmap_add_irq_chip_np() variant. Sometimes one want to register
the IRQ domain on a different device node that the one of the regmap
node. For example when using a MFD where there are different interrupt
controllers and particularly for the generic regmap gpio_chip/irq_chip
driver. In this case it is not desireable to have the IRQ domain on
the parent node.
Signed-off-by: NMichael Walle <michael@walle.cc>
Link: https://lore.kernel.org/r/20200402203656.27047-5-michael@walle.ccSigned-off-by: NMark Brown <broonie@kernel.org>

Swap selector_mask and selector_shift descriptions
Signed-off-by: NPhong LE <ple@baylibre.com>
Link: https://lore.kernel.org/r/20200219140906.29180-1-ple@baylibre.comSigned-off-by: NMark Brown <broonie@kernel.org>

This patch adds a macro 'regmap_read_poll_timeout_atomic' that works
similar to 'readx_poll_timeout_atomic' defined in linux/iopoll.h; This
is atomic version of already available 'regmap_read_poll_timeout' macro.

It should be noted that above atomic macro cannot be used by all regmaps.
If the regmap is set up for atomic use (flat or no cache and MMIO) then
only it can use.
Signed-off-by: NSameer Pujar <spujar@nvidia.com>
Link: https://lore.kernel.org/r/1578546590-24737-1-git-send-email-spujar@nvidia.comSigned-off-by: NMark Brown <broonie@kernel.org>

Based on 2 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation #

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 4122 file(s).
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Reviewed-by: NEnrico Weigelt <info@metux.net>
Reviewed-by: NKate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: NAllison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.deSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

The conversion here is really trivial: just a bunch of title
markups and very few puntual changes is enough to make it to
be parsed by Sphinx and generate a nice html.

The conversion is actually:
  - add blank lines and identation in order to identify paragraphs;
  - fix tables markups;
  - add some lists markups;
  - mark literal blocks;
  - adjust title markups.

At its new index.rst, let's add a :orphan: while this is not linked to
the main index.rst file, in order to avoid build warnings.
Signed-off-by: NMauro Carvalho Chehab <mchehab+samsung@kernel.org>
Acked-by: NMark Brown <broonie@kernel.org>
Signed-off-by: NJonathan Corbet <corbet@lwn.net>

Add basic support for i3c bus.
This is a simple implementation that only give support
for SDR Read and Write commands.
Signed-off-by: NVitor Soares <vitor.soares@synopsys.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

There is bunch of devices with multiple logical blocks which
can generate interrupts. It's not a rare case that the interrupt
reason registers are arranged so that there is own status/ack/mask
register for each logical block. In some devices there is also a
'main interrupt register(s)' which can indicate what sub blocks
have interrupts pending.

When such a device is connected via slow bus like i2c the main
part of interrupt handling latency can be caused by bus accesses.
On systems where it is expected that only one (or few) sub blocks
have active interrupts we can reduce the latency by only reading
the main register and those sub registers which have active
interrupts. Support this with regmap-irq for simple cases where
main register does not require acking or masking.
Signed-off-by: NMatti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Some interrupt controllers whose interrupts are acked on read will set
the status bits for masked interrupts without changing the state of
the IRQ line.

Some chips have an additional "feature" where if those set bits are
not cleared before unmasking their respective interrupts, the IRQ
line will change the state and we'll interpret this as an interrupt
although it actually fired when it was masked.

Add a new field to the irq chip struct that tells the regmap irq chip
code to always clear the status registers before actually changing the
irq mask values.
Signed-off-by: NBartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Add level active IRQ support to regmap-irq irqchip. Change breaks
existing regmap-irq type setting. Convert the existing drivers which
use regmap-irq with trigger type setting (gpio-max77620) to work
with this new approach. So we do not magically support level-active
IRQs on gpio-max77620 - but add support to the regmap-irq for chips
which support them =)

We do not support distinguishing situation where HW supports rising
and falling edge detection but not both. Separating this would require
inventing yet another flags for IRQ types.
Signed-off-by: NMatti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Some interrupt controllers use separate bits for controlling rising
and falling edge interrupts in the mask register i.e. they have one
interrupt for rising edge and one for falling.

We already handle the case where we have a single interrupt in the
mask register and a separate type configuration register.

Add a new switch to regmap_irq_chip which tells the framework to use
the mask_base address for configuring the edge of the interrupts that
define type_falling/rising_mask values.

For such interrupts we never update the type_base bits. For interrupts
that don't define type masks or their regmap irq chip doesn't set the
type_in_mask to true everything stays the same.
Signed-off-by: NBartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

if there are lots of irqs for a device and the register addresses for these
irqs is continuous, we can use this macro to initialize regmap_irq value.
Signed-off-by: NTony Xie <tony.xie@rock-chips.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

The regmap API had a noinc_read function added for instances where devices
supported returning data from an internal FIFO in a single read.

This commit adds the noinc_write variant to allow writing to a non
incrementing register, this is used in devices such as the sx1301 for
loading firmware.
Signed-off-by: NBen Whitten <ben.whitten@lairdtech.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Split regmap_config.use_single_rw into use_single_read and
use_single_write. This change enables drivers of devices which only
support bulk operations in one direction to use the regmap_bulk_*()
functions for both directions and have their bulk operation split into
single operations only when necessary.

Update all struct regmap_config instances where use_single_rw==true to
instead set both use_single_read and use_single_write. No attempt was
made to evaluate whether it is possible to set only one of
use_single_read or use_single_write.
Signed-off-by: NDavid Frey <dpfrey@gmail.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

The regmap API usually assumes that bulk read operations will read a
range of registers but some I2C/SPI devices have certain registers for
which a such a read operation will return data from an internal FIFO
instead. Add an explicit API to support bulk read without range semantics.

Some linux drivers use regmap_bulk_read or regmap_raw_read for such
registers, for example mpu6050 or bmi150 from IIO. This only happens to
work because when caching is disabled a single regmap read op will map
to a single bus read op (as desired). This breaks if caching is enabled and
reg+1 happens to be a cacheable register.

Without regmap support refactoring a driver to enable regmap caching
requires separate I2C and SPI paths. This is exactly what regmap is
supposed to help avoid.
Suggested-by: NJonathan Cameron <jic23@kernel.org>
Signed-off-by: NCrestez Dan Leonard <leonard.crestez@intel.com>
Signed-off-by: NStefan Popa <stefan.popa@analog.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

This adds Serial Camera Control Bus (SCCB) support for regmap API that
is intended to be used by some of Omnivision sensor drivers.

The ov772x and ov9650 drivers are going to use this SCCB regmap API.

The ov772x driver was previously only worked with the i2c controller
drivers that support I2C_FUNC_PROTOCOL_MANGLING, because the ov772x
device doesn't support repeated starts.  After commit 0b964d18
("media: ov772x: allow i2c controllers without
I2C_FUNC_PROTOCOL_MANGLING"), reading ov772x register is replaced with
issuing two separated i2c messages in order to avoid repeated start.
Using this SCCB regmap hides the implementation detail.

The ov9650 driver also issues two separated i2c messages to read the
registers as the device doesn't support repeated start.  So it can
make use of this SCCB regmap.

Cc: Mark Brown <broonie@kernel.org>
Cc: Peter Rosin <peda@axentia.se>
Cc: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Cc: Wolfram Sang <wsa@the-dreams.de>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Jacopo Mondi <jacopo+renesas@jmondi.org>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Hans Verkuil <hans.verkuil@cisco.com>
Cc: Sakari Ailus <sakari.ailus@linux.intel.com>
Cc: Mauro Carvalho Chehab <mchehab@s-opensource.com>
Signed-off-by: NAkinobu Mita <akinobu.mita@gmail.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

For some reason the devm variant of slimbus init is not added
into the header eventhough this __devm_regmap_init_slimbus()
is an exported function.

This patch adds this. This also fixes below warning in regmap-slimbus.c
regmap-slimbus.c:65:15: warning: symbol '__devm_regmap_init_slimbus'
 was not declared. Should it be static?
regmap-slimbus.c:65:16: warning: no previous prototype for
 '__devm_regmap_init_slimbus' [-Wmissing-prototypes]

Fixes: 7d6f7fb0 ("regmap: add SLIMbus support")
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: NMark Brown <broonie@kernel.org>

Similar to the readx_poll_timeout() macro calling ktime_* and using
ktime_t type, which is declared in <linux/ktime.h>. So, make
include/linux/regmap.h explicitly include <linux/ktime.h>, like
include/linux/iopoll.h does.  Otherwise, users of the macro will see
below errors.

error: implicit declaration of function ‘ktime_add_us’
[-Werror=implicit-function-declaration]

error: implicit declaration of function ‘ktime_get’
[-Werror=implicit-function-declaration]

error: implicit declaration of function ‘ktime_compare’
[-Werror=implicit-function-declaration]

include/linux/regmap.h:128:2: error: unknown type name ‘ktime_t’
  ktime_t __timeout = ktime_add_us(ktime_get(), __timeout_us); \
Signed-off-by: NSean Wang <sean.wang@mediatek.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

regmap_init_mmio_clk allows to specify a clock that needs to be enabled
while accessing the registers.

However, that clock is retrieved through its clock ID, which means it will
lookup that clock based on the current device that registers the regmap,
and, in the DT case, will only look in that device OF node.

This might be problematic if the clock to enable is stored in another node.
Let's add a function that allows to attach a clock that has already been
retrieved to a regmap in order to fix this.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

All zero read and write masks in the regmap config are used to signal no
special mask is needed and the bus defaults are used. In some devices
all zero read/write masks are the special mask and bus defaults should
not be used. To signal this a new variable is added.

For example SPI often sets bit 7 in address to signal to the device a
read is requested. On TI AFE44xx parts with SPI interfaces no bit
needs to be set as registers are either read or write only and the
operation can be determined from the address only. For this case both
masks must be zero to not effect the address.
Signed-off-by: NAndrew F. Davis <afd@ti.com>
Signed-off-by: NMark Brown <broonie@kernel.org>