1. 09 2月, 2022 1 次提交
  2. 03 2月, 2022 3 次提交
    • J
      KVM: arm64: Workaround Cortex-A510's single-step and PAC trap errata · 1dd498e5
      James Morse 提交于
      Cortex-A510's erratum #2077057 causes SPSR_EL2 to be corrupted when
      single-stepping authenticated ERET instructions. A single step is
      expected, but a pointer authentication trap is taken instead. The
      erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow
      EL1 to cause a return to EL2 with a guest controlled ELR_EL2.
      
      Because the conditions require an ERET into active-not-pending state,
      this is only a problem for the EL2 when EL2 is stepping EL1. In this case
      the previous SPSR_EL2 value is preserved in struct kvm_vcpu, and can be
      restored.
      
      Cc: stable@vger.kernel.org # 53960faf: arm64: Add Cortex-A510 CPU part definition
      Cc: stable@vger.kernel.org
      Signed-off-by: NJames Morse <james.morse@arm.com>
      [maz: fixup cpucaps ordering]
      Signed-off-by: NMarc Zyngier <maz@kernel.org>
      Link: https://lore.kernel.org/r/20220127122052.1584324-5-james.morse@arm.com
      1dd498e5
    • J
      KVM: arm64: Stop handle_exit() from handling HVC twice when an SError occurs · 1229630a
      James Morse 提交于
      Prior to commit defe21f4 ("KVM: arm64: Move PC rollback on SError to
      HYP"), when an SError is synchronised due to another exception, KVM
      handles the SError first. If the guest survives, the instruction that
      triggered the original exception is re-exectued to handle the first
      exception. HVC is treated as a special case as the instruction wouldn't
      normally be re-exectued, as its not a trap.
      
      Commit defe21f4 didn't preserve the behaviour of the 'return 1'
      that skips the rest of handle_exit().
      
      Since commit defe21f4, KVM will try to handle the SError and the
      original exception at the same time. When the exception was an HVC,
      fixup_guest_exit() has already rolled back ELR_EL2, meaning if the
      guest has virtual SError masked, it will execute and handle the HVC
      twice.
      
      Restore the original behaviour.
      
      Fixes: defe21f4 ("KVM: arm64: Move PC rollback on SError to HYP")
      Cc: stable@vger.kernel.org
      Signed-off-by: NJames Morse <james.morse@arm.com>
      Signed-off-by: NMarc Zyngier <maz@kernel.org>
      Link: https://lore.kernel.org/r/20220127122052.1584324-4-james.morse@arm.com
      1229630a
    • J
      KVM: arm64: Avoid consuming a stale esr value when SError occur · 1c71dbc8
      James Morse 提交于
      When any exception other than an IRQ occurs, the CPU updates the ESR_EL2
      register with the exception syndrome. An SError may also become pending,
      and will be synchronised by KVM. KVM notes the exception type, and whether
      an SError was synchronised in exit_code.
      
      When an exception other than an IRQ occurs, fixup_guest_exit() updates
      vcpu->arch.fault.esr_el2 from the hardware register. When an SError was
      synchronised, the vcpu esr value is used to determine if the exception
      was due to an HVC. If so, ELR_EL2 is moved back one instruction. This
      is so that KVM can process the SError first, and re-execute the HVC if
      the guest survives the SError.
      
      But if an IRQ synchronises an SError, the vcpu's esr value is stale.
      If the previous non-IRQ exception was an HVC, KVM will corrupt ELR_EL2,
      causing an unrelated guest instruction to be executed twice.
      
      Check ARM_EXCEPTION_CODE() before messing with ELR_EL2, IRQs don't
      update this register so don't need to check.
      
      Fixes: defe21f4 ("KVM: arm64: Move PC rollback on SError to HYP")
      Cc: stable@vger.kernel.org
      Reported-by: NSteven Price <steven.price@arm.com>
      Signed-off-by: NJames Morse <james.morse@arm.com>
      Signed-off-by: NMarc Zyngier <maz@kernel.org>
      Link: https://lore.kernel.org/r/20220127122052.1584324-3-james.morse@arm.com
      1c71dbc8
  3. 02 2月, 2022 1 次提交
    • M
      kvm/arm64: rework guest entry logic · 8cfe148a
      Mark Rutland 提交于
      In kvm_arch_vcpu_ioctl_run() we enter an RCU extended quiescent state
      (EQS) by calling guest_enter_irqoff(), and unmasked IRQs prior to
      exiting the EQS by calling guest_exit(). As the IRQ entry code will not
      wake RCU in this case, we may run the core IRQ code and IRQ handler
      without RCU watching, leading to various potential problems.
      
      Additionally, we do not inform lockdep or tracing that interrupts will
      be enabled during guest execution, which caan lead to misleading traces
      and warnings that interrupts have been enabled for overly-long periods.
      
      This patch fixes these issues by using the new timing and context
      entry/exit helpers to ensure that interrupts are handled during guest
      vtime but with RCU watching, with a sequence:
      
      	guest_timing_enter_irqoff();
      
      	guest_state_enter_irqoff();
      	< run the vcpu >
      	guest_state_exit_irqoff();
      
      	< take any pending IRQs >
      
      	guest_timing_exit_irqoff();
      
      Since instrumentation may make use of RCU, we must also ensure that no
      instrumented code is run during the EQS. I've split out the critical
      section into a new kvm_arm_enter_exit_vcpu() helper which is marked
      noinstr.
      
      Fixes: 1b3d546d ("arm/arm64: KVM: Properly account for guest CPU time")
      Reported-by: NNicolas Saenz Julienne <nsaenzju@redhat.com>
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Reviewed-by: NMarc Zyngier <maz@kernel.org>
      Reviewed-by: NNicolas Saenz Julienne <nsaenzju@redhat.com>
      Cc: Alexandru Elisei <alexandru.elisei@arm.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Frederic Weisbecker <frederic@kernel.org>
      Cc: James Morse <james.morse@arm.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Paul E. McKenney <paulmck@kernel.org>
      Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
      Cc: Will Deacon <will@kernel.org>
      Message-Id: <20220201132926.3301912-3-mark.rutland@arm.com>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      8cfe148a
  4. 24 1月, 2022 1 次提交
  5. 22 1月, 2022 1 次提交
  6. 14 1月, 2022 1 次提交
  7. 04 1月, 2022 1 次提交
  8. 20 12月, 2021 2 次提交
  9. 17 12月, 2021 1 次提交
  10. 16 12月, 2021 16 次提交
  11. 15 12月, 2021 8 次提交
  12. 14 12月, 2021 1 次提交
  13. 10 12月, 2021 1 次提交
  14. 08 12月, 2021 2 次提交