1. 17 12月, 2018 1 次提交
  2. 26 11月, 2018 1 次提交
  3. 17 11月, 2018 2 次提交
    • B
      gpio: mockup: fix indicated direction · bff466ba
      Bartosz Golaszewski 提交于
      Commit 3edfb7bd ("gpiolib: Show correct direction from the
      beginning") fixed an existing issue but broke libgpiod tests by
      changing the default direction of dummy lines to output.
      
      We don't break user-space so make gpio-mockup behave as before.
      Signed-off-by: NBartosz Golaszewski <brgl@bgdev.pl>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      bff466ba
    • R
      gpio: pxa: fix legacy non pinctrl aware builds again · 70cdb6ad
      Robert Jarzmik 提交于
      As pointed out by Gregor, spitz keyboard matrix is broken, with or
      without CONFIG_PINCTRL set, quoting :
      "The gpio matrix keypard on the Zaurus C3x00 (see spitz.c) does not work
      properly. Noticeable are that rshift+c does nothing where as lshift+c
      creates C.  Opposite it is for rshift+a vs lshift+a, here only rshift
      works. This affects a few other combinations using the rshift or lshift
      buttons."
      
      As a matter of fact, as for platform_data based builds CONFIG_PINCTRL=n
      is required for now (as opposed for devicetree builds where it should be
      set), this means gpio driver should change the direction, which is what
      was attempted by commit c4e5ffb6 ("gpio: pxa: fix legacy non pinctrl
      aware builds").
      
      Unfortunately, the input case was inverted, and the direction change was
      never done. This wasn't seen up until now because the initial platform
      setup (MFP) was setting this direction. Yet in Gregory's case, the
      matrix-keypad driver changes back and forth the direction dynamically,
      and this is why he's the first to report it.
      
      Fixes: c4e5ffb6 ("gpio: pxa: fix legacy non pinctrl aware builds")
      Tested-by: NGreg <greguu@null.net>
      Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      70cdb6ad
  4. 09 11月, 2018 1 次提交
  5. 16 10月, 2018 4 次提交
  6. 15 10月, 2018 1 次提交
    • R
      gpio: fix SNPS_CREG kconfig dependency warning · a7c0b4b8
      Randy Dunlap 提交于
      Fix kconfig warning for GPIO_SNPS_CREG:
      
      WARNING: unmet direct dependencies detected for OF_GPIO
        Depends on [n]: GPIOLIB [=y] && OF [=n] && HAS_IOMEM [=y]
        Selected by [y]:
        - GPIO_SNPS_CREG [=y] && GPIOLIB [=y] && HAS_IOMEM [=y] && (ARC || COMPILE_TEST [=y])
      
      Drivers in drivers/gpio/Kconfig depend on OF_GPIO, not select it.
      This prevents attempting to build when OF is not enabled.
      Signed-off-by: NRandy Dunlap <rdunlap@infradead.org>
      Cc: Linus Walleij <linus.walleij@linaro.org>
      Cc: linux-gpio@vger.kernel.org
      Cc: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      a7c0b4b8
  7. 13 10月, 2018 1 次提交
    • L
      regulator/gpio: Allow nonexclusive GPIO access · b0ce7b29
      Linus Walleij 提交于
      This allows nonexclusive (simultaneous) access to a single
      GPIO line for the fixed regulator enable line. This happens
      when several regulators use the same GPIO for enabling and
      disabling a regulator, and all need a handle on their GPIO
      descriptor.
      
      This solution with a special flag is not entirely elegant
      and should ideally be replaced by something more careful as
      this makes it possible for several consumers to
      enable/disable the same GPIO line to the left and right
      without any consistency. The current use inside the regulator
      core should however be fine as it takes special care to
      handle this.
      
      For the state of the GPIO backend, this is still the
      lesser evil compared to going back to global GPIO
      numbers.
      
      Cc: Marek Szyprowski <m.szyprowski@samsung.com>
      Cc: Jon Hunter <jonathanh@nvidia.com>
      Fixes: efdfeb07 ("regulator: fixed: Convert to use GPIO descriptor only")
      Reported-by: NMarek Szyprowski <m.szyprowski@samsung.com>
      Tested-by: NJon Hunter <jonathanh@nvidia.com>
      Tested-by: NMarek Szyprowski <m.szyprowski@samsung.com>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      b0ce7b29
  8. 12 10月, 2018 1 次提交
  9. 10 10月, 2018 6 次提交
    • S
      gpio: Assign gpio_irq_chip::parents to non-stack pointer · 3e779a2e
      Stephen Boyd 提交于
      gpiochip_set_cascaded_irqchip() is passed 'parent_irq' as an argument
      and then the address of that argument is assigned to the gpio chips
      gpio_irq_chip 'parents' pointer shortly thereafter. This can't ever
      work, because we've just assigned some stack address to a pointer that
      we plan to dereference later in gpiochip_irq_map(). I ran into this
      issue with the KASAN report below when gpiochip_irq_map() tried to setup
      the parent irq with a total junk pointer for the 'parents' array.
      
      BUG: KASAN: stack-out-of-bounds in gpiochip_irq_map+0x228/0x248
      Read of size 4 at addr ffffffc0dde472e0 by task swapper/0/1
      
      CPU: 7 PID: 1 Comm: swapper/0 Not tainted 4.14.72 #34
      Call trace:
      [<ffffff9008093638>] dump_backtrace+0x0/0x718
      [<ffffff9008093da4>] show_stack+0x20/0x2c
      [<ffffff90096b9224>] __dump_stack+0x20/0x28
      [<ffffff90096b91c8>] dump_stack+0x80/0xbc
      [<ffffff900845a350>] print_address_description+0x70/0x238
      [<ffffff900845a8e4>] kasan_report+0x1cc/0x260
      [<ffffff900845aa14>] __asan_report_load4_noabort+0x2c/0x38
      [<ffffff900897e098>] gpiochip_irq_map+0x228/0x248
      [<ffffff900820cc08>] irq_domain_associate+0x114/0x2ec
      [<ffffff900820d13c>] irq_create_mapping+0x120/0x234
      [<ffffff900820da78>] irq_create_fwspec_mapping+0x4c8/0x88c
      [<ffffff900820e2d8>] irq_create_of_mapping+0x180/0x210
      [<ffffff900917114c>] of_irq_get+0x138/0x198
      [<ffffff9008dc70ac>] spi_drv_probe+0x94/0x178
      [<ffffff9008ca5168>] driver_probe_device+0x51c/0x824
      [<ffffff9008ca6538>] __device_attach_driver+0x148/0x20c
      [<ffffff9008ca14cc>] bus_for_each_drv+0x120/0x188
      [<ffffff9008ca570c>] __device_attach+0x19c/0x2dc
      [<ffffff9008ca586c>] device_initial_probe+0x20/0x2c
      [<ffffff9008ca18bc>] bus_probe_device+0x80/0x154
      [<ffffff9008c9b9b4>] device_add+0x9b8/0xbdc
      [<ffffff9008dc7640>] spi_add_device+0x1b8/0x380
      [<ffffff9008dcbaf0>] spi_register_controller+0x111c/0x1378
      [<ffffff9008dd6b10>] spi_geni_probe+0x4dc/0x6f8
      [<ffffff9008cab058>] platform_drv_probe+0xdc/0x130
      [<ffffff9008ca5168>] driver_probe_device+0x51c/0x824
      [<ffffff9008ca59cc>] __driver_attach+0x100/0x194
      [<ffffff9008ca0ea8>] bus_for_each_dev+0x104/0x16c
      [<ffffff9008ca58c0>] driver_attach+0x48/0x54
      [<ffffff9008ca1edc>] bus_add_driver+0x274/0x498
      [<ffffff9008ca8448>] driver_register+0x1ac/0x230
      [<ffffff9008caaf6c>] __platform_driver_register+0xcc/0xdc
      [<ffffff9009c4b33c>] spi_geni_driver_init+0x1c/0x24
      [<ffffff9008084cb8>] do_one_initcall+0x240/0x3dc
      [<ffffff9009c017d0>] kernel_init_freeable+0x378/0x468
      [<ffffff90096e8240>] kernel_init+0x14/0x110
      [<ffffff9008086fcc>] ret_from_fork+0x10/0x18
      
      The buggy address belongs to the page:
      page:ffffffbf037791c0 count:0 mapcount:0 mapping:          (null) index:0x0
      flags: 0x4000000000000000()
      raw: 4000000000000000 0000000000000000 0000000000000000 00000000ffffffff
      raw: ffffffbf037791e0 ffffffbf037791e0 0000000000000000 0000000000000000
      page dumped because: kasan: bad access detected
      
      Memory state around the buggy address:
       ffffffc0dde47180: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
       ffffffc0dde47200: f1 f1 f1 f1 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f2 f2
      >ffffffc0dde47280: f2 f2 00 00 00 00 00 00 00 00 00 00 f3 f3 f3 f3
                                                             ^
       ffffffc0dde47300: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
       ffffffc0dde47380: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
      
      Let's leave around one unsigned int in the gpio_irq_chip struct for the
      single parent irq case and repoint the 'parents' array at it. This way
      code is left mostly intact to setup parents and we waste an extra few
      bytes per structure of which there should be only a handful in a system.
      
      Cc: Evan Green <evgreen@chromium.org>
      Cc: Thierry Reding <treding@nvidia.com>
      Cc: Grygorii Strashko <grygorii.strashko@ti.com>
      Fixes: e0d89728 ("gpio: Implement tighter IRQ chip integration")
      Signed-off-by: NStephen Boyd <swboyd@chromium.org>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      3e779a2e
    • U
      gpio: fix doc string for devm_gpiochip_add_data() to not talk about irq_chip · 3925b90f
      Uwe Kleine-König 提交于
      The function is about adding a gpio_chip so dev has to belong to this
      one. Fix wording to be more grammatically correct (but attention, I'm
      not a native speaker).
      Signed-off-by: NUwe Kleine-König <uwe@kleine-koenig.org>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      3925b90f
    • M
      gpio: syscon: Fix possible NULL ptr usage · 70728c29
      Marek Vasut 提交于
      The priv->data->set can be NULL while flags contains GPIO_SYSCON_FEAT_OUT
      and chip->set is valid pointer. This happens in case the controller uses
      the default GPIO setter. Always use chip->set to access the setter to avoid
      possible NULL pointer dereferencing.
      Signed-off-by: NMarek Vasut <marex@denx.de>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      70728c29
    • R
      gpiolib: Show correct direction from the beginning · 3edfb7bd
      Ricardo Ribalda Delgado 提交于
      Current code assumes that the direction is input if direction_input
      function is set.
      This might not be the case on GPIOs with programmable direction.
      Signed-off-by: NRicardo Ribalda Delgado <ricardo.ribalda@gmail.com>
      Tested-by: NJeffrey Hugo <jhugo@codeaurora.org>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      3edfb7bd
    • R
      gpiolib: Add init_valid_mask exported function · f8ec92a9
      Ricardo Ribalda Delgado 提交于
      Add a function that allows initializing the valid_mask from
      gpiochip_add_data.
      
      This prevents race conditions during gpiochip initialization.
      
      If the function is not exported, then the old behaviour is respected,
      this is, set all gpios as valid.
      Signed-off-by: NRicardo Ribalda Delgado <ricardo.ribalda@gmail.com>
      Tested-by: NJeffrey Hugo <jhugo@codeaurora.org>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      f8ec92a9
    • E
      GPIO: add single-register GPIO via CREG driver · 2505c7b0
      Eugeniy Paltsev 提交于
      Add single-register MMIO GPIO driver for complex cases where
      only several fields in register belong to GPIO lines and each GPIO
      line owns a field with different length and on/off value.
      
      Such CREG GPIOs are used in Synopsys AXS10x and HSDK boards.
      Signed-off-by: NEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      2505c7b0
  10. 03 10月, 2018 2 次提交
  11. 02 10月, 2018 1 次提交
  12. 01 10月, 2018 8 次提交
  13. 28 9月, 2018 1 次提交
  14. 25 9月, 2018 4 次提交
  15. 24 9月, 2018 6 次提交
    • T
      gpio: omap: Get rid of pm_runtime_irq_safe() · 5284521a
      Tony Lindgren 提交于
      If a gpio instance has any GPIO bits requested we do a pm_runtime_get()
      on the device. Now with cpu_pm handling the deeper SoC idle state quirks,
      let's just remove pm_runtime_irq_safe() call and add a warning in case we
      ever happen to encounter it.
      
      Cc: Aaro Koskinen <aaro.koskinen@iki.fi>
      Cc: Keerthy <j-keerthy@ti.com>
      Cc: Ladislav Michl <ladis@linux-mips.org>
      Cc: Tero Kristo <t-kristo@ti.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      Acked-by: NGrygorii Strashko <grygorii.strashko@ti.com>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      5284521a
    • T
      gpio: omap: Remove custom PM calls and use cpu_pm instead · b764a586
      Tony Lindgren 提交于
      For a long time the gpio-omap custom PM calls have been annoying me so
      let's replace them with cpu_pm instead. This will enable GPIO PM for
      deeper idle states on omap4. And we can handle GPIO PM for omap2/3/4
      in the same way.
      
      Note that with this patch we are also slightly changing GPIO PM to be
      less aggressive for omap3 and only will idle GPIO when PER context
      may be lost.
      
      For omap2, we don't need to save context and don't want to remove any
      triggering so let's add a quirk flag for that.
      
      Let's do this all in a single patch to avoid a situation where old
      custom calls still are used with new code.
      
      Cc: Aaro Koskinen <aaro.koskinen@iki.fi>
      Cc: Keerthy <j-keerthy@ti.com>
      Cc: Ladislav Michl <ladis@linux-mips.org>
      Cc: Tero Kristo <t-kristo@ti.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      Acked-by: NGrygorii Strashko <grygorii.strashko@ti.com>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      b764a586
    • T
      gpio: omap: Add level wakeup handling for omap4 based SoCs · ec0daae6
      Tony Lindgren 提交于
      I noticed that unlike omap2 and 3 based SoCs, omap4 based SoCs keep
      the GPIO clocks enabled for GPIO level interrupts with wakeup enabled.
      This blocks deeper idle states as the whole domain will stay busy.
      
      The GPIO functional clock seems to stay enabled if the wakeup register
      is enabled and a level interrupt is triggered. In that case the only
      way to have the GPIO module idle is to reset it. It is possible this
      has gone unnoticed with OSWR (Open SWitch Retention) and off mode
      during idle resetting GPIO context most GPIO instances in the earlier
      Android trees for example.
      
      Looks like the way to deal with this is to have omap4 based SoCs
      only set wake for the duration of idle for level interrupts, and clear
      level registers for the idle. With level interrupts we can do this as
      the level interrupt from device will be still there on resume.
      
      I've taken the long path to fixing this to avoid yet more hard to
      read code. I've set up a quirks flag, and a struct for function
      pointers so we can use these to clean up other quirk handling easier
      in the later patches. The current level quirk handling is moved to
      the new functions.
      
      Cc: Aaro Koskinen <aaro.koskinen@iki.fi>
      Cc: Ladislav Michl <ladis@linux-mips.org>
      Cc: Tero Kristo <t-kristo@ti.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      Acked-by: NGrygorii Strashko <grygorii.strashko@ti.com>
      Tested-by: NKeerthy <j-keerthy@ti.com>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      ec0daae6
    • J
      gpiolib: Fix array members of same chip processed separately · c4c958aa
      Janusz Krzysztofik 提交于
      New code introduced by commit bf9346f5 ("gpiolib: Identify arrays
      matching GPIO hardware") forcibly tries to find an array member which
      has its array index number equal to its hardware pin number and set
      up an array info for possible fast bitmap processing of all arrray
      pins belonging to that chip which also satisfy that numbering rule.
      
      Depending on array content, it may happen that consecutive array
      members which belong to the same chip but don't have array indexes
      equal to their pin hardware numbers will be split into groups, some of
      them processed together via the fast bitmap path, and rest of them
      separetely.  However, applications may expect all those pins being
      processed together with a single call to .set_multiple() chip callback,
      like that was done before the change.
      
      Limit applicability of fast bitmap processing path to cases where all
      pins of consecutive array members starting from 0 which belong to the
      same chip have their hardware numbers equal to their corresponding
      array indexes.  That should still speed up processing of applications
      using whole GPIO banks as I/O ports, while not breaking simultaneous
      manipulation of consecutive pins of the same chip which don't follow
      the equal numbering rule.
      
      Cc: Jonathan Corbet <corbet@lwn.net>
      Signed-off-by: NJanusz Krzysztofik <jmkrzyszt@gmail.com>
      Tested-by: NMarek Szyprowski <m.szyprowski@samsung.com>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      c4c958aa
    • J
      gpiolib: Fix missing updates of bitmap index · 35ae7f96
      Janusz Krzysztofik 提交于
      In new code introduced by commit b17566a6 ("gpiolib: Implement fast
      processing path in get/set array"), bitmap index is not updated with
      next found zero bit position as it should while skipping over pins
      already processed via fast bitmap path, possibly resulting in an
      infinite loop.  Fix it.
      Signed-off-by: NJanusz Krzysztofik <jmkrzyszt@gmail.com>
      Tested-by: NMarek Szyprowski <m.szyprowski@samsung.com>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      35ae7f96
    • L
      gpio: htc-egpio: Unique label per chip · 212d7069
      Linus Walleij 提交于
      Give the HTC EGPIO chips unique names, htc-egpio-0,
      htc-egpio-1 etc, so that it gets possible to associate
      machine descriptor tables with individual chips.
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      212d7069