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  1. 04 12月, 2019 1 次提交
  3. 20 11月, 2019 1 次提交
  5. 14 11月, 2019 1 次提交
  7. 13 11月, 2019 1 次提交
  9. 12 11月, 2019 1 次提交
  11. 11 11月, 2019 1 次提交
  13. 08 11月, 2019 1 次提交
  15. 07 11月, 2019 1 次提交
  17. 05 11月, 2019 2 次提交
  19. 01 11月, 2019 2 次提交
  21. 31 10月, 2019 2 次提交
  23. 30 10月, 2019 1 次提交
  25. 28 10月, 2019 1 次提交
  27. 26 10月, 2019 1 次提交
  29. 23 10月, 2019 1 次提交
  31. 19 10月, 2019 2 次提交
  33. 17 10月, 2019 1 次提交
  35. 15 10月, 2019 4 次提交
    • V
      drm/i915: Switch to using DP_MSA_MISC_* defines · 3e706dff
      由 Ville Syrjälä 提交于 
      Now that we have standard defines for the MSA MISC bits lets use
them on HSW+ where we program these directly into the TRANS_MSA_MISC
register.
Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190718145053.25808-7-ville.syrjala@linux.intel.comReviewed-by: NGwan-gyeong Mun <gwan-gyeong.mun@intel.com>
      3e706dff
    • G
      drm/i915/dp: Program an Infoframe SDP Header and DB for HDR Static Metadata · b246cf21
      由 Gwan-gyeong Mun 提交于 
      Function intel_dp_setup_hdr_metadata_infoframe_sdp handles Infoframe SDP
header and data block setup for HDR Static Metadata. It enables writing of
HDR metadata infoframe SDP to panel. Support for HDR video was introduced
in DisplayPort 1.4. It implements the CTA-861-G standard for transport of
static HDR metadata. The HDR Metadata will be provided by userspace
compositors, based on blending policies and passed to the driver through
a blob property.

Because each of GEN11 and prior GEN11 have different register size for
HDR Metadata Infoframe SDP packet, it adds and uses different register
size.

Setup Infoframe SDP header and data block in function
intel_dp_setup_hdr_metadata_infoframe_sdp for HDR Static Metadata as per
dp 1.4 spec and CTA-861-F spec.
As per DP 1.4 spec, 2.2.2.5 SDP Formats. It enables Dynamic Range and
Mastering Infoframe for HDR content, which is defined in CTA-861-F spec.
According to DP 1.4 spec and CEA-861-F spec Table 5, in order to transmit
static HDR metadata, we have to use Non-audio INFOFRAME SDP v1.3.

+--------------------------------+-------------------------------+
|      [ Packet Type Value ]     |       [ Packet Type ]         |
+--------------------------------+-------------------------------+
| 80h + Non-audio INFOFRAME Type | CEA-861-F Non-audio INFOFRAME |
+--------------------------------+-------------------------------+
|      [Transmission Timing]                                     |
+----------------------------------------------------------------+
| As per CEA-861-F for INFOFRAME, including CEA-861.3 within     |
| which Dynamic Range and Mastering INFOFRAME are defined        |
+----------------------------------------------------------------+

v2: Add a missed blank line after function declaration.
v3: Remove not handled return values from
    intel_dp_setup_hdr_metadata_infoframe_sdp(). [Uma]
v9: Addressed review comments from Ville.
    - Add BUILD_BUG_ON to check a changing of struct dp_sdp size.
    - Change a passed size toward write_infoframe() for DP infoframe sdp
      packet for HDR static metadata.
Signed-off-by: NGwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: NUma Shankar <uma.shankar@intel.com>
Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190919195311.13972-8-gwan-gyeong.mun@intel.com
      b246cf21
    • G
      drm/i915/dp: Add support of BT.2020 Colorimetry to DP MSA · 0c06fa15
      由 Gwan-gyeong Mun 提交于 
      When BT.2020 Colorimetry output is used for DP, we should program BT.2020
Colorimetry to MSA and VSC SDP. In order to handle colorspace of
drm_connector_state, it moves a calling of intel_ddi_set_pipe_settings()
function into intel_ddi_pre_enable_dp(). And it also rename
intel_ddi_set_pipe_settings() to intel_ddi_set_dp_msa().

As per DP 1.4a spec section 2.2.4 [MSA Data Transport]
The MSA data that the DP Source device transports for reproducing the main
video stream. Attribute data is sent once per frame during the main video
stream’s vertical blanking period.

In order to distinguish needed colorimetry for VSC SDP, it adds
intel_dp_needs_vsc_sdp function.
If the output colorspace requires vsc sdp or output format is YCbCr 4:2:0,
it uses MSA with VSC SDP.

As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication of
Color Encoding Format and Content Color Gamut] while sending
BT.2020 Colorimetry signals we should program MSA MISC1 fields which
indicate VSC SDP for the Pixel Encoding/Colorimetry Format.

v2: Remove useless parentheses
v3: Addressed review comments from Ville
    - In order to checking output format and output colorspace on
      intel_dp_needs_vsc_sdp(), it passes entire intel_crtc_state struct
      value.
    - Remove a pointless variable.
v9: Addressed review comments from Ville
    - Remove a duplicated output color space from intel_crtc_state.
    - In order to handle colorspace of drm_connector_state, it moves a
      calling of intel_ddi_set_pipe_settings() function into
      intel_ddi_pre_enable_dp().
Signed-off-by: NGwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: NUma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190919195311.13972-3-gwan-gyeong.mun@intel.comSigned-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      0c06fa15
    • G
      drm/i915/dp: Extend program of VSC Header and DB for Colorimetry Format · bb71fb00
      由 Gwan-gyeong Mun 提交于 
      It refactors and renames a function which handled vsc sdp header and data
block setup for supporting colorimetry format.
Function intel_dp_setup_vsc_sdp handles vsc sdp header and data block
setup for pixel encoding / colorimetry format.
In order to use colorspace information of a connector, it adds an argument
of drm_connector_state type.

Setup VSC header and data block in function intel_dp_setup_vsc_sdp for
pixel encoding / colorimetry format as per dp 1.4a spec, section 2.2.5.7.1,
table 2-119: VSC SDP Header Bytes, section 2.2.5.7.5,
table 2-120: VSC SDP Payload for DB16 through DB18.
Signed-off-by: NGwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: NUma Shankar <uma.shankar@intel.com>
Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190919195311.13972-2-gwan-gyeong.mun@intel.com
      bb71fb00
  37. 08 10月, 2019 1 次提交
    • A
      drm/i915/tgl: Do modeset to enable and configure DC3CO exitline · bdacf087
      由 Anshuman Gupta 提交于 
      DC3CO enabling B.Specs sequence requires to enable end configure
exit scanlines to TRANS_EXITLINE register, programming this register
has to be part of modeset sequence as this can't be change when
transcoder or port is enabled.
When system boots with only eDP panel there may not be real
modeset as BIOS has already programmed the necessary registers,
therefore it needs to force a modeset to enable and configure
DC3CO exitline.

v1: Computing dc3co_exitline crtc state from a DP encoder
    compute config. [Imre]
    Enabling and disabling DC3CO PSR2 transcoder exitline from
    encoder pre_enable and post_disable hooks. [Imre]
    Computing dc3co_exitline instead of has_dc3co_exitline bool. [Imre]
v2: Code refactoring for symmetry and to avoid exported function. [Imre]
    Removing IS_TIGERLAKE check from compute_config, adding PIPE_A
    restriction and clearing dc3co_exitline state if crtc is not active
    or it is not PSR2 capable in dc3co exitline compute_config. [Imre]
    Using GEN >= 12 check in dc3co exitline get_config. [Imre]

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: NImre Deak <imre.deak@intel.com>
Signed-off-by: NAnshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: NImre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191003081738.22101-5-anshuman.gupta@intel.com
      bdacf087
  39. 03 10月, 2019 1 次提交
  41. 28 9月, 2019 2 次提交
  43. 26 9月, 2019 2 次提交
  45. 25 9月, 2019 1 次提交
  47. 24 9月, 2019 2 次提交
  49. 21 9月, 2019 2 次提交
  51. 05 9月, 2019 2 次提交
  53. 02 9月, 2019 1 次提交
  55. 27 8月, 2019 1 次提交