Smatch complains that the dev_err_ratelimited() is indented one tab more
than the surrounding lines.

	drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu_cmn.c:174
	__smu_cmn_reg_print_error() warn: inconsistent indenting

It looks like it's not a bug, just that the indenting needs to be cleaned
up.
Reviewed-by: NLuben Tuikov <luben.tuikov@amd.com>
Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Various spelling mistakes in comments.
Detected with the help of Coccinelle.
Signed-off-by: NJulia Lawall <Julia.Lawall@inria.fr>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Various spelling mistakes in comments.
Detected with the help of Coccinelle.
Signed-off-by: NJulia Lawall <Julia.Lawall@inria.fr>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Various spelling mistakes in comments.
Detected with the help of Coccinelle.
Signed-off-by: NJulia Lawall <Julia.Lawall@inria.fr>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

MI25 SRIOV guest driver loading failed due to allocated memory overlaps
with firmware reserved area.
Allocate stolen reserved memory for MI25 SRIOV specifically to avoid the
memory overlap.
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NYongqiang Sun <yongqiang.sun@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Some ASICs need reserved memory for firmware or other components,
which is not allowed to be used by driver.
amdgpu_gmc_get_reserved_allocation is to handle additional areas.
To avoid any missing calling,
merged amdgpu_gmc_get_reserved_allocation to
amdgpu_gmc_get_vbios_allocations.
Acked-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NYongqiang Sun <yongqiang.sun@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Migrate vram to ram may fail to find the vma if process is exiting
and vma is removed, evict svm bo worker sets prange->svm_bo to NULL
and warn svm_bo ref count != 1 only if migrating vram to ram
successfully.
Signed-off-by: NPhilip Yang <Philip.Yang@amd.com>
Reviewed-by: NFelix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
On Renoir, vcn ring test failed on the second time insmod in the reload
test. After investigation, it proves that vcn only can disable dpg under
dpg unpause mode (dpg unpause mode is default for dec only, dpg pause
mode is for dec/enc).

[how]
unpause dpg in dpg stopping procedure.
Reviewed-by: NJames Zhu <James.Zhu@amd.com>
Signed-off-by: NTianci Yin <tianci.yin@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Only GFX ring, SDMA ring and VCN decode ring support secure submission
at the moment.
Suggested-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NLang Yu <Lang.Yu@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

The reported warnings are as follows:
  1.warning:no-previous-prototype-for-amdgpu_hdp_ras_fini.
  2.warning:no-previous-prototype-for-amdgpu_mmhub_ras_fini.

Amdgpu_hdp_ras_fini and amdgpu_mmhub_ras_fini are unused
in the code, they are the only functions in amdgpu_hdp.c
and amdgpu_mmhub.c. After removing these two functions,
both amdgpu_hdp.c and amdgpu_mmhub.c are empty, so these
two files can be deleted to fix the warning.
Signed-off-by: Nyipechai <YiPeng.Chai@amd.com>
Reviewed-by: NTao Zhou <tao.zhou1@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

    This version brings along following fixes:
    - Added I2C escape to support query exist
    - Functionality to get pipe from stream context
    - debugfs entry fixes
    - Block zstate when more than one plane enabled
    - Update to engine ddc
    - Reading lante status during LT fixes
    - Null point filters
    - [FW Promotion] Release 0.0.108.0
Acked-by: NAgustin Gutierrez <agustin.gutierrez@amd.com>
Signed-off-by: NAric Cyr <aric.cyr@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NAgustin Gutierrez <agustin.gutierrez@amd.com>
Signed-off-by: NAnthony Koo <Anthony.Koo@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
DCN31 has this in zstate save/restore sequence.
need for non_zstate supported ASIC

[how]
add this PANEL_PWRSEQ_REF_DIV2 to existing panel_cntl_hw_init structure.
Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: NAgustin Gutierrez <agustin.gutierrez@amd.com>
Signed-off-by: NCharlene Liu <Charlene.Liu@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Underflow occurred while hubp ret pipe read is idle and the
second pipe is powered up and added. Flickering and underflow
are only observed on Pollock.

[How]
Check the hubp ret pipe read prior to unlock pipes.
Reviewed-by: NHersen Wu <hersenxs.wu@amd.com>
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NAgustin Gutierrez <agustin.gutierrez@amd.com>
Signed-off-by: NBecle Lee <becle.lee@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
Add null pointer filter for logical integrity.
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NAgustin Gutierrez <agustin.gutierrez@amd.com>
Signed-off-by: NJing Zhou <Jing.Zhou@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
In dp_get_lane_status_and_lane_adjust(), we call core_link_read_dpcd()
to get lane status but we ignore the return value of the function. If
there is problem with AUX and we eventually can only get partial data
from monitor, we might misuse the data to jude the link training result.
Which could have us trapped in the dc_link_dp_perform_link_training()
since we thought that we can still give a try on another link setting.

[How]
In dp_get_lane_status_and_lane_adjust(), take return value of
core_link_read_dpcd() into account. If we fail to read all requested
data, we treat lanes status as previous one and repeat LT steps again.
Reviewed-by: NWenjing Liu <Wenjing.Liu@amd.com>
Acked-by: NAgustin Gutierrez <agustin.gutierrez@amd.com>
Signed-off-by: NWayne Lin <Wayne.Lin@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
We must support a new type of partial edid return in the future

[How]
Add interface and case hander for partial edid
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NAgustin Gutierrez <agustin.gutierrez@amd.com>
Signed-off-by: NDale Zhao <dale.zhao@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Currently Z10 save/restore only covers 1 plane case. If we enter
Z10 with 2 planes enabled, 1 of the 2 planes will not be restored.
causing black screen.

[How]
Disable Zstate when more than 1 plane is enabled. Right now Z9 enable
but Z10 disable is not a supported config, so we disable both.
Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Reviewed-by: NNevenko Stupar <Nevenko.Stupar@amd.com>
Acked-by: NAgustin Gutierrez <agustin.gutierrez@amd.com>
Signed-off-by: NEric Yang <Eric.Yang2@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Crash caused by a ddc update failure

[How]
Update engine ddc before release engine.
Reviewed-by: NWyatt Wood <Wyatt.Wood@amd.com>
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NAgustin Gutierrez <agustin.gutierrez@amd.com>
Signed-off-by: NJing Zhou <Jing.Zhou@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
1. To leverage and simplify the igt tool. Change the value of
retrain when calling preferred training settings.
Now, writing value to link settings triggers link training immediately.

2. Add dc lock when triggering link training in edp_ilr_write()
Reviewed-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: NAgustin Gutierrez <agustin.gutierrez@amd.com>
Signed-off-by: NWayne Lin <Wayne.Lin@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
We need a helper function in dc to grab the pipe from the stream
context.

[How]
Add it.
Reviewed-by: NMartin Leung <Martin.Leung@amd.com>
Acked-by: NAgustin Gutierrez <agustin.gutierrez@amd.com>
Signed-off-by: NLeo (Hanghong) Ma <hanghong.ma@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[How]
1. Search OEM I2C info from BIOS and compare with input parameter.
2. If BIOS doesn't record it, just try to read one byte.
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NAgustin Gutierrez <agustin.gutierrez@amd.com>
Signed-off-by: NJinZe.Xu <JinZe.Xu@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

amdgpu_detect_virtualization reads register, amdgpu_device_rreg access
adev->reset_domain->sem if kernel defined CONFIG_LOCKDEP, below is the
random boot hang backtrace on Vega10. It may get random NULL pointer
access backtrace if amdgpu_sriov_runtime is true too.

Move amdgpu_reset_create_reset_domain before calling to RREG32.

 BUG: kernel NULL pointer dereference, address:
 #PF: supervisor read access in kernel mode
 #PF: error_code(0x0000) - not-present page
 PGD 0 P4D 0
 Oops: 0000 [#1] PREEMPT SMP NOPTI
 Workqueue: events work_for_cpu_fn
 RIP: 0010:down_read_trylock+0x13/0xf0
 Call Trace:
  <TASK>
  amdgpu_device_skip_hw_access+0x38/0x80 [amdgpu]
  amdgpu_device_rreg+0x1b/0x170 [amdgpu]
  amdgpu_detect_virtualization+0x73/0x100 [amdgpu]
  amdgpu_device_init.cold.60+0xbe/0x16b1 [amdgpu]
  ? pci_bus_read_config_word+0x43/0x70
  amdgpu_driver_load_kms+0x15/0x120 [amdgpu]
  amdgpu_pci_probe+0x1a1/0x3a0 [amdgpu]

Fixes: d0fb18b5 ("drm/amdgpu: Move reset sem into reset_domain")
Signed-off-by: NPhilip Yang <Philip.Yang@amd.com>
Reviewed-by: NAndrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
CP hangs in igt reloading test on renoir, more precisely, hangs on the
second time insmod.

[how]
mode2 reset can make it recover, and mode2 reset only effects gfx core,
dcn and the screen will not be impacted.
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NTianci.Yin <tianci.yin@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

We don't support runtime pm on APUs.  They support more
dynamic power savings using clock and powergating.
Reviewed-by: NMario Limonciello <mario.limonciello@amd.com>
Tested-by: NMario Limonciello <mario.limonciello@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NStanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: NEvan Quan <evan.quan@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

xgmi_ras is only initialized when host to GPU interface
is PCIE. in such case, xgmi23 is disabled and protected
by security firmware. Host access will results to
security violation
Signed-off-by: NHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: NTao Zhou <tao.zhou1@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

VFs must also distinguish whether or not the TA supports full duplex or
half duplex link records in order to report the correct xGMI topology.
Signed-off-by: NJonathan Kim <jonathan.kim@amd.com>
Reviewed-by: NShaoyun Liu <shaoyun.liu@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Enable scatter/gather display for DCN 3.1.6.
Reviewed-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
To debug when p-state is being blocked and avoid PMFW hangs when
it does occur.

[How]
Re-use the DCN10 hardware sequencer by adding a new interface for
verifying p-state high on the hubbub. The interface is mostly the
same as the DCN10 interface, but the bit definitions have changed for
the debug bus.
Signed-off-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: NEric Yang <Eric.Yang2@amd.com>
Reviewed-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Export dmabuf handles for GTT BOs so that their contents can be accessed
using SDMA during checkpoint/restore.

v2: Squash in fix from David to set dmabuf handle to invalid for BOs
that cannot be accessed using SDMA during checkpoint/restore.
Signed-off-by: NDavid Yat Sin <david.yatsin@amd.com>
Reviewed-by : Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Refactor CRIU restore BO to reduce identation.
Signed-off-by: NDavid Yat Sin <david.yatsin@amd.com>
Reviewed-by: NFelix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

When the process is getting restored, the queues are not mapped yet, so
there is no VMID assigned for this process and no TLBs to flush.
Signed-off-by: NDavid Yat Sin <david.yatsin@amd.com>
Reviewed-by: NFelix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
The DP KVM failed to light up, since the lttpr_mode is not reset to
default value when failed to read LTTPR capabilities, and the
variable max_link_rate retains a initial value zero, this cause variable
link_rate be assigned to an error value zero, consquently pixel_clock
get wrong value zero, and kvm can't light up.

[how]
Reset lttpr_mode to default value when failed to read LTTPR
capabilities, so that the link_rate fallbacks to the minimum rate that
supported by link encoder and sink.
Reviewed-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NTianci.Yin <tianci.yin@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

When PMFW is really busy, it will respond with 0xFC. However, it doesn't
change the response register state when it becomes free. Driver should
retry and proceed to send message if the response status is 0xFC.
Signed-off-by: NLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: NEvan Quan <evan.quan@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

It should notice SMU to update bad channel info when detected
uncorrectable error in UMC block
Signed-off-by: NStanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: NTao Zhou <tao.zhou1@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

support message SMU update bad channel info to update HBM bad channel
info in OOB table
Signed-off-by: NStanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: NTao Zhou <tao.zhou1@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

FPU operations in dcn10 was already moved to dml folder via calcs code.
However, dcn1_0_ip and dcn_1_0_soc with FPU componentd remains on dcn10.
Following previous changes to isolate FPU, this patch creates dcn10_fpu
files to isolate FPU-specific code and moves those structs to it.
Signed-off-by: NMelissa Wen <mwen@igalia.com>
Acked-by: NAlan Liu <HaoPing.Liu@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

dml/dcn20_fpu file centralizes all DCN2x functions that require FPU access.
Therefore, this patch moves FPU-related code from dcn21 to dcn20_fpu. These
include:
- dcn21_populate_dml_pipes_from_context()
- dcn21_validate_bandwidth_fp() and related:
  - dcn21_calculate_wm(),
  - patch_bounding_box(),
  - calculate_wm_set_for_vlevel()
- renaming update_bw_bounding_box() to dcn21_update_bw_bounding_box(), move
to dcn20_fpu with related static function construct_low_pstate_lvl()

Also, make dcn21_fast_validate_bw() public in dcn21_resource as it is called
by dcn21_validate_bandwidth_fp() now in dcn20_fpu.

Reuse dcn20_fpu_adjust_dppclk() in dcn21_fast_validate_bw() as it isolates
the same FPU operation.

Include dchubbub.h as it is required in dcn21_populate_dml_pipes_from_context()
Signed-off-by: NMelissa Wen <mwen@igalia.com>
Acked-by: NAlan Liu <HaoPing.Liu@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Move parts of dcn20 code that uses FPU to dml folder. It aims to isolate
FPU operations as described by series:

drm/amd/display: Introduce FPU directory inside DC
https://patchwork.freedesktop.org/series/93042/

This patch moves the following functions from dcn20_resource to
dml/dcn20_fpu and calls of public functions in dcn20_resource are
wrapped by DC_FP_START/END():

- void dcn20_populate_dml_writeback_from_context
- static bool is_dtbclk_required()
- static enum dcn_zstate_support_state()
- void dcn20_calculate_dlg_params()
- static void swizzle_to_dml_params()
- int dcn20_populate_dml_pipes_from_context()
- void dcn20_calculate_wm()
- void dcn20_cap_soc_clocks()
- void dcn20_update_bounding_box()
- void dcn20_patch_bounding_box()
- bool dcn20_validate_bandwidth_fp()

This movement also affects dcn21/30/31, as dcn20_calculate_dlg_params()
is used by them. For this reason, I included dcn20_fpu headers in
dcn20_resource headers to make dcn20_calculate_dlg_params() visible to
dcn21/30/31.

Three new functions are created to isolate well-delimited FPU
operations:

- void dcn20_fpu_set_wb_arb_params(): set cli_watermark,
  pstate_watermark and time_per_pixel from wb_arb_params (struct
mcif_arb_params), since those uses FPU operations on double types:
WritebackUrgentWatermark, WritebackDRAMClockChangeWatermark, '16.0'.
- void dcn20_fpu_set_wm_ranges(): set min_fill_clk_mhz and
  max_fill_clk_mhz involves FPU calcs on dram_speed_mts (double type);
- void dcn20_fpu_adjust_dppclk(): adjust operation on RequiredDPPCLK
  that is a double.
Signed-off-by: NMelissa Wen <mwen@igalia.com>
Acked-by: NAlan Liu <HaoPing.Liu@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>