Skip to content

K
Kernel

openeuler / Kernel
接近 2 年 前同步成功

通知 8
Star 0
Fork 0
K
Kernel
切换分支/标签
  1. 15 11月, 2013 2 次提交
  3. 11 11月, 2013 9 次提交
    • A
      ARM: dts: i.MX51: Fix OTG PHY clock · 036e2991
      由 Alexander Shiyan 提交于 
      Proper clock ID for USB OTG PHY is "usb_phy_gate".
The patch changes this mismatch.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      036e2991
    • S
      ARM: imx: set up pllv3 POWER and BYPASS sequentially · 43c9b9e8
      由 Shawn Guo 提交于 
      Currently, POWER and BYPASS bits are set up in a single write to pllv3
register.  This causes problem occasionally from the IPU/HDMI testing.
Let's follow FSL BSP code to set up POWER bit, relock, and then BYPASS
sequentially.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      43c9b9e8
    • S
      ARM: imx: pllv3 needs relock in .set_rate() call · bc3b84da
      由 Shawn Guo 提交于 
      The pllv3 nees relock not only when powering up but also when rate
changes.  The patch creates a helper function clk_pllv3_wait_lock() and
moves the relock code from clk_pllv3_prepare() into there, so that
both .prepare() and .set_rate() hooks of pllv3 can call into the helper
for relocking.

Since relock is only needed when PLL is powered up while clk_set_rate()
could be called before clk is prepared, we need to add a check in
clk_pllv3_wait_lock() to skip the relock if PLL is not powered.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      bc3b84da
    • S
      ARM: imx: add sleep for pllv3 relock · 322503a1
      由 Shawn Guo 提交于 
      The pllv3 relock time varies in the range of 50us ~ 500us, depending on
the specific PLL type, e.g. 50us for ARM PLL and 450us for Audio/Video
PLL.  Let's add a usleep_range() call instead of doing busy wait during
relock.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      322503a1
    • L
      ARM: imx6q: add missing sentinel to divider table · ec9de6cd
      由 Lothar Waßmann 提交于 
      The clk_enet_ref_table[] is missing a final empty entry as end of list
marker. Also make the existing markers more obvious.
Signed-off-by: NLothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      ec9de6cd
    • S
      ARM: imx: v7_cpu_resume() is needed by imx6sl build · 5d482172
      由 Shawn Guo 提交于 
      Building a kernel with the following options,

  CONFIG_SMP=n
  CONFIG_PM=y
  CONFIG_SOC_IMX6SL=y
  CONFIG_SOC_IMX6Q=n

we will see the build error below.

  arch/arm/mach-imx/built-in.o: In function `imx6q_pm_enter':
  platform-spi_imx.c:(.text+0x2648): undefined reference to `v7_cpu_resume'
  make[1]: *** [vmlinux] Error 1

This is because that v7_cpu_resume() implemented in headsmp.S is also
needed by imx6sl build.  Let's build headsmp.S for CONFIG_SOC_IMX6SL as
well.
Reported-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      5d482172
    • S
      ARM: imx: improve mxc_restart() on the SRC bit writes · 2c11b57a
      由 Shawn Guo 提交于 
      The current comment in the code does not make it clear why the double writes
on SRC bit is needed.  Let's quote the errata to get it clear.  Also, to
ensure there are at least 2 writes happen in the same one 32kHz period,
we actually need 3 writes.  Let's add the third one.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      2c11b57a
    • S
      ARM: imx: remove imx_src_prepare_restart() call · b6e23bb6
      由 Shawn Guo 提交于 
      There is ~10% possibility that the following emergency restart command
fails to reboot imx6q.

$ echo b > /proc/sysrq-trigger

The IMX restart routine mxc_restart() assumes that it will always run on
primary core, and will call imx_src_prepare_restart() to disable
secondary cores in order to get them come to online in the following
boot.  However, the assumption is only true for normal kernel_restart()
case where migrate_to_reboot_cpu() will be called to migrate to primary
core, but not necessarily true for emergency_restart() case.  So when
emergency_restart() calls into mxc_restart() on any secondary core,
system will hang immediately once imx_src_prepare_restart() is called
to disabled secondary cores.  Since emergency_restart() is defined as a
function that is safe to call in interrupt context, we cannot just call
migrate_to_reboot_cpu() to fix the issue.

Fortunately, we just found that the issue can be fixed at imx6q platform
level.  We used to call imx_src_prepare_restart() to disable all
secondary cores before resetting hardware.  Otherwise, the secondary
will fail come to online in the reboot.  However, we recently found that
after commit 6050d181 (ARM: imx: reset core along with enable/disable
operation) comes to play, we do not need to reset the secondary cores
any more.  That said, mxc_restart() now can run on any core to reboot
the system, as long as we remove the imx_src_prepare_restart() call from
mxc_restart().

So let's simply remove imx_src_prepare_restart() call to fix the above
emergency restart failure.
Reported-by: NJiada Wang <jiada_wang@mentor.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      b6e23bb6
    • J
      ARM: i.MX6q: fix the wrong parent of can_root clock · 9b3d4237
      由 Jiada Wang 提交于 
      instead of pll3_usb_otg the parent of can_root clock
should be pll3_60m.
Signed-off-by: NJiada Wang <jiada_wang@mentor.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      9b3d4237
  5. 01 11月, 2013 5 次提交
  7. 31 10月, 2013 4 次提交
  9. 30 10月, 2013 15 次提交
  11. 29 10月, 2013 4 次提交
  13. 23 10月, 2013 1 次提交