1. 26 1月, 2021 20 次提交
  2. 24 1月, 2021 15 次提交
  3. 23 1月, 2021 5 次提交
    • J
      Merge branch 'mlxsw-expose-number-of-physical-ports' · 59a49d96
      Jakub Kicinski 提交于
      Ido Schimmel says:
      
      ====================
      mlxsw: Expose number of physical ports
      
      The switch ASIC has a limited capacity of physical ports that it can
      support. While each system is brought up with a different number of
      ports, this number can be increased via splitting up to the ASIC's
      limit.
      
      Expose physical ports as a devlink resource so that user space will have
      visibility into the maximum number of ports that can be supported and
      the current occupancy. With this resource it is possible, for example,
      to write generic (i.e., not platform dependent) tests for port
      splitting.
      
      Patch #1 adds the new resource and patch #2 adds a selftest.
      
      v2:
      * Add the physical ports resource as a generic devlink resource so that
        it could be re-used by other device drivers
      ====================
      
      Link: https://lore.kernel.org/r/20210121131024.2656154-1-idosch@idosch.orgSigned-off-by: NJakub Kicinski <kuba@kernel.org>
      59a49d96
    • D
      selftests: mlxsw: Add a scale test for physical ports · 5154b1b8
      Danielle Ratson 提交于
      Query the maximum number of supported physical ports using devlink-resource
      and test that this number can be reached by splitting each of the
      splittable ports to its width. Test that an error is returned in case
      the maximum number is exceeded.
      Signed-off-by: NDanielle Ratson <danieller@nvidia.com>
      Signed-off-by: NIdo Schimmel <idosch@nvidia.com>
      Signed-off-by: NJakub Kicinski <kuba@kernel.org>
      5154b1b8
    • D
      mlxsw: Register physical ports as a devlink resource · 321f7ab0
      Danielle Ratson 提交于
      The switch ASIC has a limited capacity of physical ('flavour physical'
      in devlink terminology) ports that it can support. While each system is
      brought up with a different number of ports, this number can be
      increased via splitting up to the ASIC's limit.
      
      Expose physical ports as a devlink resource so that user space will have
      visibility to the maximum number of ports that can be supported and the
      current occupancy.
      
      In addition, add a "Generic Resources" section in devlink-resource
      documentation so the different drivers will be aligned by the same resource
      name when exposing to user space.
      Signed-off-by: NDanielle Ratson <danieller@nvidia.com>
      Reviewed-by: NJiri Pirko <jiri@nvidia.com>
      Signed-off-by: NIdo Schimmel <idosch@nvidia.com>
      Signed-off-by: NJakub Kicinski <kuba@kernel.org>
      321f7ab0
    • J
      Merge branch 'htb-offload' · 35187642
      Jakub Kicinski 提交于
      Maxim Mikityanskiy says:
      
      ====================
      HTB offload
      
      This series adds support for HTB offload to the HTB qdisc, and adds
      usage to mlx5 driver.
      
      The previous RFCs are available at [1], [2].
      
      The feature is intended to solve the performance bottleneck caused by
      the single lock of the HTB qdisc, which prevents it from scaling well.
      The HTB algorithm itself is offloaded to the device, eliminating the
      need to take the root lock of HTB on every packet. Classification part
      is done in clsact (still in software) to avoid acquiring the lock, which
      imposes a limitation that filters can target only leaf classes.
      
      The speedup on Mellanox ConnectX-6 Dx was 14.2 times in the UDP
      multi-stream test, compared to software HTB implementation (more details
      in the mlx5 patch).
      
      [1]: https://www.spinics.net/lists/netdev/msg628422.html
      [2]: https://www.spinics.net/lists/netdev/msg663548.html
      
      v2 changes:
      
      Fixed sparse and smatch warnings. Formatted HTB patches to 80 chars per
      line.
      
      v3 changes:
      
      Fixed the CI failure on parisc with 16-bit xchg by replacing it with
      WRITE_ONCE. Fixed the capability bits in mlx5_ifc.h and the value of
      MLX5E_QOS_MAX_LEAF_NODES.
      
      v4 changes:
      
      Check if HTB is root when offloading. Add extack for hardware errors.
      Rephrase explanations of how it works in the commit message. Remove %hu
      from format strings. Add resiliency when leaf_del_last fails to create a
      new leaf node.
      ====================
      
      Link: https://lore.kernel.org/r/20210119120815.463334-1-maximmi@mellanox.comSigned-off-by: NJakub Kicinski <kuba@kernel.org>
      35187642
    • M
      net/mlx5e: Support HTB offload · 214baf22
      Maxim Mikityanskiy 提交于
      This commit adds support for HTB offload in the mlx5e driver.
      
      Performance:
      
        NIC: Mellanox ConnectX-6 Dx
        CPU: Intel(R) Xeon(R) CPU E5-2680 v3 @ 2.50GHz (24 cores with HT)
      
        100 Gbit/s line rate, 500 UDP streams @ ~200 Mbit/s each
        48 traffic classes, flower used for steering
        No shaping (rate limits set to 4 Gbit/s per TC) - checking for max
        throughput.
      
        Baseline: 98.7 Gbps, 8.25 Mpps
        HTB: 6.7 Gbps, 0.56 Mpps
        HTB offload: 95.6 Gbps, 8.00 Mpps
      
      Limitations:
      
      1. 256 leaf nodes, 3 levels of depth.
      
      2. Granularity for ceil is 1 Mbit/s. Rates are converted to weights, and
      the bandwidth is split among the siblings according to these weights.
      Other parameters for classes are not supported.
      
      Ethtool statistics support for QoS SQs are also added. The counters are
      called qos_txN_*, where N is the QoS queue number (starting from 0, the
      numeration is separate from the normal SQs), and * is the counter name
      (the counters are the same as for the normal SQs).
      Signed-off-by: NMaxim Mikityanskiy <maximmi@mellanox.com>
      Reviewed-by: NTariq Toukan <tariqt@nvidia.com>
      Signed-off-by: NJakub Kicinski <kuba@kernel.org>
      214baf22