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  1. 23 7月, 2012 1 次提交
  3. 06 6月, 2012 1 次提交
  5. 13 5月, 2012 8 次提交
  7. 12 5月, 2012 1 次提交
  9. 20 4月, 2012 1 次提交
  11. 27 3月, 2012 2 次提交
    • H
      mxs-dma : rewrite the last parameter of mxs_dma_prep_slave_sg() · 921de864
      由 Huang Shijie 提交于 
      [1] Background :
    The GPMI does ECC read page operation with a DMA chain consist of three DMA
    Command Structures. The middle one of the chain is used to enable the BCH,
    and read out the NAND page.

    The WAIT4END(wait for command end) is a comunication signal between
    the GPMI and MXS-DMA.

[2] The current DMA code sets the WAIT4END bit at the last one, such as:

    +-----+               +-----+                      +-----+
    | cmd | ------------> | cmd | ------------------>  | cmd |
    +-----+               +-----+                      +-----+
                                                          ^
                                                          |
                                                          |
                                                     set WAIT4END here

    This chain works fine in the mx23/mx28.

[3] But in the new GPMI version (used in MX50/MX60), the WAIT4END bit should
    be set not only at the last DMA Command Structure,
    but also at the middle one, such as:

    +-----+               +-----+                      +-----+
    | cmd | ------------> | cmd | ------------------>  | cmd |
    +-----+               +-----+                      +-----+
                             ^                            ^
                             |                            |
                             |                            |
                        set WAIT4END here too        set WAIT4END here

    If we do not set WAIT4END, the BCH maybe stalls in "ECC reading page" state.
    In the next ECC write page operation, a DMA-timeout occurs.
    This has been catched in the MX6Q board.

[4] In order to fix the bug, rewrite the last parameter of mxs_dma_prep_slave_sg(),
    and use the dma_ctrl_flags:
    ---------------------------------------------------------
      DMA_PREP_INTERRUPT : append a new DMA Command Structrue.
      DMA_CTRL_ACK       : set the WAIT4END bit for this DMA Command Structure.
    ---------------------------------------------------------

[5] changes to the relative drivers:
    <1> For mxs-mmc driver, just use the new flags, do not change any logic.
    <2> For gpmi-nand driver, and use the new flags to set the DMA
        chain, especially for ecc read page.
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NHuang Shijie <b32955@freescale.com>
Acked-by: NVinod Koul <vinod.koul@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
      921de864
    • H
      mxs-dma : move the mxs dma.h to a more common place · 39468604
      由 Huang Shijie 提交于 
      Move the header to a more common place.
The mxs dma engine is not only used in mx23/mx28, but also used
in mx50/mx6q.  It will also be used in the future chips.

Rename it to mxs-dma.h, and create a new folder include/linux/fsl/ to
store the Freescale's header files.

change mxs-dma driver, mxs-mmc driver, gpmi-nand driver, mxs-saif driver
to the new header file.
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Acked-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: NHuang Shijie <b32955@freescale.com>
Acked-by: NVinod Koul <vinod.koul@linux.intel.com>
Acked-by: NChris Ball <cjb@laptop.org>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
      39468604
  13. 21 3月, 2012 1 次提交
  15. 12 1月, 2012 1 次提交
  17. 28 12月, 2011 1 次提交
  19. 24 12月, 2011 1 次提交
  21. 31 10月, 2011 1 次提交
  23. 27 10月, 2011 1 次提交
  25. 21 7月, 2011 1 次提交
    • K
      mmc: mxs-mmc: fix clock rate setting · d982dcdc
      由 Koen Beel 提交于 
      Fix clock rate setting in the mxs-mmc driver. Previously, if div2 was 0
then the value for TIMING_CLOCK_RATE would have been 255 instead of 0.
The limits for div1 (TIMING_CLOCK_DIVIDE) and div2 (TIMING_CLOCK_RATE+1)
were also not correctly defined.

Can easily be reproduced on mx23evk: default clock for high speed sdio
cards is 50 MHz. With a SSP_CLK of 28.8 MHz default), this resulted in
an actual clock rate of about 56 kHz.  Tested on mx23evk.
Signed-off-by: NKoen Beel <koen.beel@barco.com>
Reviewed-by: NWolfram Sang <w.sang@pengutronix.de>
Signed-off-by: NChris Ball <cjb@laptop.org>
      d982dcdc
  27. 16 3月, 2011 1 次提交