提交 · 4c66b56781eb114d478d8488e614a4f832a44a2c · openeuler / Kernel

07 1月, 2022 3 次提交

selftests: KVM: sev_migrate_tests: Fix test_sev_mirror() · 4c66b567

由 Peter Gonda 提交于 12月 08, 2021

Mirrors should not be able to call LAUNCH_START. Remove the call on the
mirror to correct the test before fixing sev_ioctl() to correctly assert
on this failed ioctl.

Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Sean Christopherson <seanjc@google.com>
Cc: Marc Orr <marcorr@google.com>
Signed-off-by: NPeter Gonda <pgonda@google.com>
Message-Id: <20211208191642.3792819-2-pgonda@google.com>
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>

4c66b567

Merge tag 'kvm-riscv-5.17-1' of https://github.com/kvm-riscv/linux into HEAD · 1b0c9d00

由 Paolo Bonzini 提交于 1月 07, 2022

KVM/riscv changes for 5.17, take #1

- Use common KVM implementation of MMU memory caches
- SBI v0.2 support for Guest
- Initial KVM selftests support
- Fix to avoid spurious virtual interrupts after clearing hideleg CSR
- Update email address for Anup and Atish

1b0c9d00

Merge tag 'kvmarm-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD · 7fd55a02

由 Paolo Bonzini 提交于 1月 07, 2022

KVM/arm64 updates for Linux 5.16

- Simplification of the 'vcpu first run' by integrating it into
  KVM's 'pid change' flow

- Refactoring of the FP and SVE state tracking, also leading to
  a simpler state and less shared data between EL1 and EL2 in
  the nVHE case

- Tidy up the header file usage for the nvhe hyp object

- New HYP unsharing mechanism, finally allowing pages to be
  unmapped from the Stage-1 EL2 page-tables

- Various pKVM cleanups around refcounting and sharing

- A couple of vgic fixes for bugs that would trigger once
  the vcpu xarray rework is merged, but not sooner

- Add minimal support for ARMv8.7's PMU extension

- Rework kvm_pgtable initialisation ahead of the NV work

- New selftest for IRQ injection

- Teach selftests about the lack of default IPA space and
  page sizes

- Expand sysreg selftest to deal with Pointer Authentication

- The usual bunch of cleanups and doc update

7fd55a02

06 1月, 2022 14 次提交

MAINTAINERS: Update Anup's email address · 497685f2

由 Anup Patel 提交于 1月 03, 2022

I am no longer work at Western Digital so update my email address to
personal one and add entries to .mailmap as well.
Signed-off-by: NAnup Patel <anup@brainfault.org>
Acked-by: NAtish Patra <atishp@rivosinc.com>

497685f2

KVM: RISC-V: Avoid spurious virtual interrupts after clearing hideleg CSR · 33e5b574

由 Vincent Chen 提交于 12月 27, 2021

When the last VM is terminated, the host kernel will invoke function
hardware_disable_nolock() on each CPU to disable the related virtualization
functions. Here, RISC-V currently only clears hideleg CSR and hedeleg CSR.
This behavior will cause the host kernel to receive spurious interrupts if
hvip CSR has pending interrupts and the corresponding enable bits in vsie
CSR are asserted. To avoid it, hvip CSR and vsie CSR must be cleared
before clearing hideleg CSR.

Fixes: 99cdc6c1 ("RISC-V: Add initial skeletal KVM support")
Signed-off-by: NVincent Chen <vincent.chen@sifive.com>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>
Signed-off-by: NAnup Patel <anup.patel@wdc.com>

33e5b574

KVM: selftests: Add initial support for RISC-V 64-bit · 3e06cdf1

由 Anup Patel 提交于 10月 05, 2021

We add initial support for RISC-V 64-bit in KVM selftests using
which we can cross-compile and run arch independent tests such as:
demand_paging_test
dirty_log_test
kvm_create_max_vcpus,
kvm_page_table_test
set_memory_region_test
kvm_binary_stats_test

All VM guest modes defined in kvm_util.h require at least 48-bit
guest virtual address so to use KVM RISC-V selftests hardware
need to support at least Sv48 MMU for guest (i.e. VS-mode).
Signed-off-by: NAnup Patel <anup.patel@wdc.com>
Reviewed-and-tested-by: NAtish Patra <atishp@rivosinc.com>

3e06cdf1

KVM: selftests: Add EXTRA_CFLAGS in top-level Makefile · 788490e7

由 Anup Patel 提交于 11月 26, 2021

We add EXTRA_CFLAGS to the common CFLAGS of top-level Makefile which will
allow users to pass additional compile-time flags such as "-static".
Signed-off-by: NAnup Patel <anup.patel@wdc.com>
Reviewed-and-tested-by: NAtish Patra <atishp@rivosinc.com>
Reviewed-and-tested-by: NSean Christopherson <seanjc@google.com>

788490e7

RISC-V: KVM: Add VM capability to allow userspace get GPA bits · a457fd56

由 Anup Patel 提交于 11月 26, 2021

The number of GPA bits supported for a RISC-V Guest/VM is based on the
MMU mode used by the G-stage translation. The KVM RISC-V will detect and
use the best possible MMU mode for the G-stage in kvm_arch_init().

We add a generic VM capability KVM_CAP_VM_GPA_BITS which can be used by
the KVM userspace to get the number of GPA (guest physical address) bits
supported for a Guest/VM.
Signed-off-by: NAnup Patel <anup.patel@wdc.com>
Reviewed-and-tested-by: NAtish Patra <atishp@rivosinc.com>

a457fd56

RISC-V: KVM: Forward SBI experimental and vendor extensions · ef8949a9

由 Anup Patel 提交于 11月 26, 2021

The SBI experimental extension space is for temporary (or experimental)
stuff whereas SBI vendor extension space is for hardware vendor specific
stuff. Both these SBI extension spaces won't be standardized by the SBI
specification so let's blindly forward such SBI calls to the userspace.
Signed-off-by: NAnup Patel <anup.patel@wdc.com>
Reviewed-and-tested-by: NAtish Patra <atishp@rivosinc.com>

ef8949a9

RISC-V: KVM: make kvm_riscv_vcpu_fp_clean() static · 637ad655

由 Jisheng Zhang 提交于 11月 29, 2021

There are no users outside vcpu_fp.c so make kvm_riscv_vcpu_fp_clean()
static.
Signed-off-by: NJisheng Zhang <jszhang@kernel.org>
Signed-off-by: NAnup Patel <anup.patel@wdc.com>

637ad655

MAINTAINERS: Update Atish's email address · 4abed558

由 Atish Patra 提交于 12月 02, 2021

I am no longer employed by western digital. Update my email address to
personal one and add entries to .mailmap as well.
Signed-off-by: NAtish Patra <atishp@atishpatra.org>
Signed-off-by: NAnup Patel <anup.patel@wdc.com>

4abed558

RISC-V: KVM: Add SBI HSM extension in KVM · 3e1d8656