1. 01 3月, 2010 4 次提交
    • A
      KVM: PPC: Make large pages work · 4b5c9b7f
      Alexander Graf 提交于
      An SLB entry contains two pieces of information related to size:
      
        1) PTE size
        2) SLB size
      
      The L bit defines the PTE be "large" (usually means 16MB),
      SLB_VSID_B_1T defines that the SLB should span 1 GB instead of the
      default 256MB.
      
      Apparently I messed things up and just put those two in one box,
      shaked it heavily and came up with the current code which handles
      large pages incorrectly, because it also treats large page SLB entries
      as "1TB" segment entries.
      
      This patch splits those two features apart, making Linux guests boot
      even when they have > 256MB.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      Signed-off-by: NAvi Kivity <avi@redhat.com>
      4b5c9b7f
    • A
      KVM: PPC: Emulate trap SRR1 flags properly · 25a8a02d
      Alexander Graf 提交于
      Book3S needs some flags in SRR1 to get to know details about an interrupt.
      
      One such example is the trap instruction. It tells the guest kernel that
      a program interrupt is due to a trap using a bit in SRR1.
      
      This patch implements above behavior, making WARN_ON behave like WARN_ON.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      Signed-off-by: NAvi Kivity <avi@redhat.com>
      25a8a02d
    • A
      KVM: PPC: Call SLB patching code in interrupt safe manner · 021ec9c6
      Alexander Graf 提交于
      Currently we're racy when doing the transition from IR=1 to IR=0, from
      the module memory entry code to the real mode SLB switching code.
      
      To work around that I took a look at the RTAS entry code which is faced
      with a similar problem and did the same thing:
      
        A small helper in linear mapped memory that does mtmsr with IR=0 and
        then RFIs info the actual handler.
      
      Thanks to that trick we can safely take page faults in the entry code
      and only need to be really wary of what to do as of the SLB switching
      part.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      Signed-off-by: NAvi Kivity <avi@redhat.com>
      021ec9c6
    • A
      KVM: PPC: Use PACA backed shadow vcpu · 7e57cba0
      Alexander Graf 提交于
      We're being horribly racy right now. All the entry and exit code hijacks
      random fields from the PACA that could easily be used by different code in
      case we get interrupted, for example by a #MC or even page fault.
      
      After discussing this with Ben, we figured it's best to reserve some more
      space in the PACA and just shove off some vcpu state to there.
      
      That way we can drastically improve the readability of the code, make it
      less racy and less complex.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      Signed-off-by: NAvi Kivity <avi@redhat.com>
      7e57cba0
  2. 08 12月, 2009 1 次提交
  3. 05 11月, 2009 1 次提交