- 23 11月, 2022 39 次提交
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由 Suzuki K Poulose 提交于
mainline inclusion from mainline-v5.15-rc3 commit 7037a39d category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210923143919.2944311-3-suzuki.poulose@arm.com -------------------------------------------------------------------------- On a spurious IRQ, right now we disable the TRBE and then re-enable it back, resetting the "buffer" pointers(i.e BASE, LIMIT and more importantly WRITE) to the original pointers from the AUX handle. This implies that we overwrite any trace that was written so far, (by overwriting TRBPTR) while we should have ignored the IRQ. On detecting a spurious IRQ after examining the TRBSR we simply re-enable the TRBE without touching the other parameters. Cc: Anshuman Khandual <anshuman.khandual@arm.com> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Cc: Leo Yan <leo.yan@linaro.org> Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20210923143919.2944311-3-suzuki.poulose@arm.comSigned-off-by: NMathieu Poirier <mathieu.poirier@linaro.org>
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由 Suzuki K Poulose 提交于
mainline inclusion from mainline-v5.15-rc3 commit 85fb9235 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210923143919.2944311-2-suzuki.poulose@arm.com -------------------------------------------------------------------------- The IRQ handler of the TRBE driver could race against the update_buffer() in consuming the IRQ. So, if the update_buffer() gets to processing the TRBE irq, the TRBSR will be cleared. Thus by the time IRQ handler is triggered, there is nothing to do there. Handle these cases and do not disable the TRBE unnecessarily. Since the TRBSR can be read without stopping the TRBE, we can check that before disabling the TRBE. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Anshuman Khandual <anshuman.khandual@arm.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20210923143919.2944311-2-suzuki.poulose@arm.comSigned-off-by: NMathieu Poirier <mathieu.poirier@linaro.org>
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由 Suzuki K Poulose 提交于
mainline inclusion from mainline-v5.15-rc3 commit 04a37a17 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210914102641.1852544-9-suzuki.poulose@arm.com -------------------------------------------------------------------------- Unify the sequence of enabling the TRBE. We do this from event_start and also from the TRBE IRQ handler. Lets move this to a common helper. The only minor functional change is returning an error when we fail to enable the TRBE. This should be handled already. Since we now have unique entry point to trying to enable TRBE, move the format flag setting to the central place. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Cc: Leo Yan <leo.yan@linaro.org> Reviewed-by: NAnshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20210914102641.1852544-9-suzuki.poulose@arm.comSigned-off-by: NMathieu Poirier <mathieu.poirier@linaro.org>
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由 Suzuki K Poulose 提交于
mainline inclusion from mainline-v5.15-rc3 commit acee3ef8 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210914102641.1852544-6-suzuki.poulose@arm.com -------------------------------------------------------------------------- We mark the buffer as TRUNCATED when there is no space left in the buffer. But we do it at different points. __trbe_normal_offset() and also, at all the callers of the above function via compute_trbe_buffer_limit(), when the limit == base (i.e offset = 0 as returned by the __trbe_normal_offset()). So, given that the callers already mark the buffer as TRUNCATED drop the caller inside the __trbe_normal_offset(). This is in preparation to moving the handling of TRUNCATED into a central place. Cc: Anshuman Khandual <anshuman.khandual@arm.com> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Cc: Leo Yan <leo.yan@linaro.org> Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Reviewed-by: NAnshuman Khandual <anshuman.khandual@arm.com> Link: https://lore.kernel.org/r/20210914102641.1852544-6-suzuki.poulose@arm.com [Moved comment as Anshuman requested] Signed-off-by: NMathieu Poirier <mathieu.poirier@linaro.org>
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由 Suzuki K Poulose 提交于
mainline inclusion from mainline-v5.15-rc3 commit 5bd9ff83 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210914102641.1852544-5-suzuki.poulose@arm.com -------------------------------------------------------------------------- When the TRBE is stopped on truncating an event, we may not set the FORMAT flag, even though the size of the record is 0. Let us be consistent and not confuse the user. To ensure that the format flag is always set on all the records generated by TRBE, set the flag when we have a new handle. Rather than deferring to the "end" operation, which makes it clear. So, we can do this from - arm_trbe_enable() -> When a new handle is provided by the CoreSight PMU, triggered via etm_event_start() - trbe_handle_overflow() -> When we begin a new handle after closing the previous on overflow. Cc: Anshuman Khandual <anshuman.khandual@arm.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Reviewed-by: NAnshuman Khandual <anshuman.khandual@arm.com> Link: https://lore.kernel.org/r/20210914102641.1852544-5-suzuki.poulose@arm.com [Fixed inverted words in title] Signed-off-by: NMathieu Poirier <mathieu.poirier@linaro.org>
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由 Suzuki K Poulose 提交于
mainline inclusion from mainline-v5.15-rc3 commit 2ef43054 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210914102641.1852544-4-suzuki.poulose@arm.com -------------------------------------------------------------------------- The ETM perf infrastructure closes out a handle during event_stop or on an error in starting the event. In either case, it is possible for a "sink" to update/close the handle, under certain circumstances. (e.g no space in ring buffer.). So, ensure that we handle this gracefully in the PMU driver by verifying the handle is still valid. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Cc: Anshuman Khandual <anshuman.khandual@arm.com> Cc: Leo Yan <leo.yan@linaro.org> Reviewed-by: NAnshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20210914102641.1852544-4-suzuki.poulose@arm.comSigned-off-by: NMathieu Poirier <mathieu.poirier@linaro.org>
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由 Suzuki K Poulose 提交于
mainline inclusion from mainline-v5.15-rc3 commit 5f6fd1aa category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210914102641.1852544-3-suzuki.poulose@arm.com -------------------------------------------------------------------------- The Trace Filtering support (FEAT_TRF) ensures that the ETM can be prohibited from generating any trace for a given EL. This is much stricter knob, than the TRCVICTLR exception level masks, which doesn't prevent the ETM from generating Context packets for an "excluded" EL. At the moment, we do a onetime enable trace at user and kernel and leave it untouched for the kernel life time. This implies that the ETM could potentially generate trace packets containing the kernel addresses, and thus leaking the kernel virtual address in the trace. This patch makes the switch dynamic, by honoring the filters set by the user and enforcing them in the TRFCR controls. We also rename the cpu_enable_tracing() appropriately to cpu_detect_trace_filtering() and the drvdata member trfc => trfcr to indicate the "value" of the TRFCR_EL1. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Al Grant <al.grant@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Leo Yan <leo.yan@linaro.org> Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Reviewed-by: NAnshuman Khandual <anshuman.khandual@arm.com> Link: https://lore.kernel.org/r/20210914102641.1852544-3-suzuki.poulose@arm.comSigned-off-by: NMathieu Poirier <mathieu.poirier@linaro.org>
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由 Suzuki K Poulose 提交于
mainline inclusion from mainline-v5.15-rc3 commit 937d3f58 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210914102641.1852544-2-suzuki.poulose@arm.com -------------------------------------------------------------------------- When the CPU enters a low power mode, the TRFCR_EL1 contents could be reset. Thus we need to save/restore the TRFCR_EL1 along with the ETM4x registers to allow the tracing. The TRFCR related helpers are in a new header file, as we need to use them for TRBE in the later patches. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Anshuman Khandual <anshuman.khandual@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Leo Yan <leo.yan@linaro.org> Reviewed-by: NAnshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20210914102641.1852544-2-suzuki.poulose@arm.com [Fixed cosmetic details] Signed-off-by: NMathieu Poirier <mathieu.poirier@linaro.org>
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由 Suzuki K Poulose 提交于
mainline inclusion from mainline-v5.12-rc3 commit 8b481196 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210405164307.1720226-9-suzuki.poulose@arm.com -------------------------------------------------------------------------- If the CPU implements Arm v8.4 Trace filter controls (FEAT_TRF), move the ETM to trace prohibited region using TRFCR, while disabling. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Cc: Anshuman Khandual <anshuman.khandual@arm.com> Reviewed-by: NMike Leach <mike.leach@linaro.org> Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20210405164307.1720226-9-suzuki.poulose@arm.comSigned-off-by: NMathieu Poirier <mathieu.poirier@linaro.org>
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由 James Clark 提交于
mainline inclusion from mainline-v5.15-rc3 commit 8c60acbc category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210922125144.133872-2-james.clark@arm.com -------------------------------------------------------------------------- When a traced process runs on a CPU that can't reach the selected sink, the event will be stopped with PERF_HES_STOPPED. This means that even if the process migrates to a valid CPU, tracing will not resume. This can be reproduced (on N1SDP) by using taskset to start the process on CPU 0, and then switching it to CPU 2 (ETF 1 is only reachable from CPU 2): taskset --cpu-list 0 ./perf record -e cs_etm/@tmc_etf1/ --per-thread -- taskset --cpu-list 2 ls This produces a single 0 length AUX record, and then no more trace: 0x3c8 [0x30]: PERF_RECORD_AUX offset: 0 size: 0 flags: 0x1 [T] After the fix, the same command produces normal AUX records. The perf self test "89: Check Arm CoreSight trace data recording and synthesized samples" no longer fails intermittently. This was because the taskset in the test is after the fork, so there is a period where the task is scheduled on a random CPU rather than forced to a valid one. Specifically selecting an invalid CPU will still result in a failure to open the event because it will never produce trace: ./perf record -C 2 -e cs_etm/@tmc_etf0/ failed to mmap with 12 (Cannot allocate memory) The only scenario that has changed is if the CPU mask has a valid CPU sink combo in it. Testing ======= * Coresight self test passes consistently: ./perf test Coresight * CPU wide mode still produces trace: ./perf record -e cs_etm// -a * Invalid -C options still fail to open: ./perf record -C 2,3 -e cs_etm/@tmc_etf0/ failed to mmap with 12 (Cannot allocate memory) * Migrating a task to a valid sink/CPU now produces trace: taskset --cpu-list 0 ./perf record -e cs_etm/@tmc_etf1/ --per-thread -- taskset --cpu-list 2 ls * If the task remains on an invalid CPU, no trace is emitted: taskset --cpu-list 0 ./perf record -e cs_etm/@tmc_etf1/ --per-thread -- ls Reviewed-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: NJames Clark <james.clark@arm.com> Link: https://lore.kernel.org/r/20210922125144.133872-2-james.clark@arm.comSigned-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: NMathieu Poirier <mathieu.poirier@linaro.org>
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由 Leo Yan 提交于
mainline inclusion from mainline-v5.15-rc3 commit 0abd0762 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210905032144.966766-1-leo.yan@linaro.org -------------------------------------------------------------------------- The AUX bounce buffer is allocated with API dma_alloc_coherent(), in the low level's architecture code, e.g. for Arm64, it maps the memory with the attribution "Normal non-cacheable"; this can be concluded from the definition for pgprot_dmacoherent() in arch/arm64/include/asm/pgtable.h. Later when access the AUX bounce buffer, since the memory mapping is non-cacheable, it's low efficiency due to every load instruction must reach out DRAM. This patch changes to allocate pages with dma_alloc_noncoherent(), the driver can access the memory via cacheable mapping; therefore, load instructions can fetch data from cache lines rather than always read data from DRAM, the driver can boost memory performance. After using the cacheable mapping, the driver uses dma_sync_single_for_cpu() to invalidate cacheline prior to read bounce buffer so can avoid read stale trace data. By measurement the duration for function tmc_update_etr_buffer() with ftrace function_graph tracer, it shows the performance significant improvement for copying 4MiB data from bounce buffer: # echo tmc_etr_get_data_flat_buf > set_graph_notrace // avoid noise # echo tmc_update_etr_buffer > set_graph_function # echo function_graph > current_tracer before: # CPU DURATION FUNCTION CALLS # | | | | | | | 2) | tmc_update_etr_buffer() { ... 2) # 8148.320 us | } after: # CPU DURATION FUNCTION CALLS # | | | | | | | 2) | tmc_update_etr_buffer() { ... 2) # 2525.420 us | } Signed-off-by: NLeo Yan <leo.yan@linaro.org> Reviewed-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20210905032144.966766-1-leo.yan@linaro.orgSigned-off-by: NMathieu Poirier <mathieu.poirier@linaro.org>
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由 Suzuki K Poulose 提交于
mainline inclusion from mainline-v5.12-rc3 commit cc427cbb category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210405164307.1720226-6-suzuki.poulose@arm.com -------------------------------------------------------------------------- Rather than falling to an "unhandled access", inject add an explicit "undefined access" for TRFCR_EL1 access from the guest. Cc: Marc Zyngier <maz@kernel.org> Cc: Will Deacon <will@kernel.org> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Acked-by: NMarc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210405164307.1720226-6-suzuki.poulose@arm.comSigned-off-by: NMathieu Poirier <mathieu.poirier@linaro.org>
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由 Anshuman Khandual 提交于
mainline inclusion from mainline-v5.12-rc3 commit 3fbf7f01 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210405164307.1720226-18-suzuki.poulose@arm.com -------------------------------------------------------------------------- Trace Buffer Extension (TRBE) implements a trace buffer per CPU which is accessible via the system registers. The TRBE supports different addressing modes including CPU virtual address and buffer modes including the circular buffer mode. The TRBE buffer is addressed by a base pointer (TRBBASER_EL1), an write pointer (TRBPTR_EL1) and a limit pointer (TRBLIMITR_EL1). But the access to the trace buffer could be prohibited by a higher exception level (EL3 or EL2), indicated by TRBIDR_EL1.P. The TRBE can also generate a CPU private interrupt (PPI) on address translation errors and when the buffer is full. Overall implementation here is inspired from the Arm SPE driver. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: NAnshuman Khandual <anshuman.khandual@arm.com> [ Mark the buffer truncated on WRAP event, error code cleanup ] Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20210405164307.1720226-18-suzuki.poulose@arm.comSigned-off-by: NMathieu Poirier <mathieu.poirier@linaro.org>
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由 Suzuki K Poulose 提交于
mainline inclusion from mainline-v5.12-rc3 commit 547b6098 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210405164307.1720226-2-suzuki.poulose@arm.com -------------------------------------------------------------------------- Allocate a byte for advertising the PMU specific format type of the given AUX record. A PMU could end up providing hardware trace data in multiple format in a single session. e.g, The format of hardware buffer produced by CoreSight ETM PMU depends on the type of the "sink" device used for collection for an event (Traditional TMC-ETR/Bs with formatting or TRBEs without any formatting). # Boring story of why this is needed. Goto The_End_of_Story for skipping. CoreSight ETM trace allows instruction level tracing of Arm CPUs. The ETM generates the CPU excecution trace and pumps it into CoreSight AMBA Trace Bus and is collected by a different CoreSight component (traditionally CoreSight TMC-ETR /ETB/ETF), called "sink". Important to note that there is no guarantee that every CPU has a dedicated sink. Thus multiple ETMs could pump the trace data into the same "sink" and thus they apply additional formatting of the trace data for the user to decode it properly and attribute the trace data to the corresponding ETM. However, with the introduction of Arm Trace buffer Extensions (TRBE), we now have a dedicated per-CPU architected sink for collecting the trace. Since the TRBE is always per-CPU, it doesn't apply any formatting of the trace. The support for this driver is under review [1]. Now a system could have a per-cpu TRBE and one or more shared TMC-ETRs on the system. A user could choose a "specific" sink for a perf session (e.g, a TMC-ETR) or the driver could automatically select the nearest sink for a given ETM. It is possible that some ETMs could end up using TMC-ETR (e.g, if the TRBE is not usable on the CPU) while the others using TRBE in a single perf session. Thus we now have "formatted" trace collected from TMC-ETR and "unformatted" trace collected from TRBE. However, we don't get into a situation where a single event could end up using TMC-ETR & TRBE. i.e, any AUX buffer is guaranteed to be either RAW or FORMATTED, but not a mix of both. As for perf decoding, we need to know the type of the data in the individual AUX buffers, so that it can set up the "OpenCSD" (library for decoding CoreSight trace) decoder instance appropriately. Thus the perf.data file must conatin the hints for the tool to decode the data correctly. Since this is a runtime variable, and perf tool doesn't have a control on what sink gets used (in case of automatic sink selection), we need this information made available from the PMU driver for each AUX record. # The_End_of_Story Cc: Peter Ziljstra <peterz@infradead.org> Cc: alexander.shishkin@linux.intel.com Cc: mingo@redhat.com Cc: will@kernel.org Cc: mark.rutland@arm.com Cc: mike.leach@linaro.org Cc: acme@kernel.org Cc: jolsa@redhat.com Cc: Mathieu Poirier <mathieu.poirer@linaro.org> Reviewed by: Mike Leach <mike.leach@linaro.org> Acked-by: NPeter Ziljstra <peterz@infradead.org> Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20210405164307.1720226-2-suzuki.poulose@arm.comSigned-off-by: NMathieu Poirier <mathieu.poirier@linaro.org>
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由 Suzuki K Poulose 提交于
mainline inclusion from mainline-v5.12-rc3 commit 7dde5176 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210405164307.1720226-3-suzuki.poulose@arm.com -------------------------------------------------------------------------- CoreSight PMU supports aux-buffer for the ETM tracing. The trace generated by the ETM (associated with individual CPUs, like Intel PT) is captured by a separate IP (CoreSight TMC-ETR/ETF until now). The TMC-ETR applies formatting of the raw ETM trace data, as it can collect traces from multiple ETMs, with the TraceID to indicate the source of a given trace packet. Arm Trace Buffer Extension is new "sink" IP, attached to individual CPUs and thus do not provide additional formatting, like TMC-ETR. Additionally, a system could have both TRBE *and* TMC-ETR for the trace collection. e.g, TMC-ETR could be used as a single trace buffer to collect data from multiple ETMs to correlate the traces from different CPUs. It is possible to have a perf session where some events end up collecting the trace in TMC-ETR while the others in TRBE. Thus we need a way to identify the type of the trace for each AUX record. Define the trace formats exported by the CoreSight PMU. We don't define the flags following the "ETM" as this information is available to the user when issuing the session. What is missing is the additional formatting applied by the "sink" which is decided at the runtime and the user may not have a control on. So we define : - CORESIGHT format (indicates the Frame format) - RAW format (indicates the format of the source) The default value is CORESIGHT format for all the records (i,e == 0). Add the RAW format for others that use raw format. Cc: Peter Zijlstra <peterz@infradead.org> Cc: Mike Leach <mike.leach@linaro.org> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Leo Yan <leo.yan@linaro.org> Cc: Anshuman Khandual <anshuman.khandual@arm.com> Reviewed-by: NMike Leach <mike.leach@linaro.org> Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20210405164307.1720226-3-suzuki.poulose@arm.comSigned-off-by: NMathieu Poirier <mathieu.poirier@linaro.org>
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由 Suzuki K Poulose 提交于
mainline inclusion from mainline-v5.12-rc3 commit be968269 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210405164307.1720226-4-suzuki.poulose@arm.com -------------------------------------------------------------------------- tsb csync synchronizes the trace operation of instructions. The instruction is a nop when FEAT_TRF is not implemented. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Acked-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20210405164307.1720226-4-suzuki.poulose@arm.comSigned-off-by: NMathieu Poirier <mathieu.poirier@linaro.org>
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由 Anshuman Khandual 提交于
mainline inclusion from mainline-v5.12-rc3 commit 2cd87a7b category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210405164307.1720226-17-suzuki.poulose@arm.com -------------------------------------------------------------------------- Add support for dedicated sinks that are bound to individual CPUs. (e.g, TRBE). To allow quicker access to the sink for a given CPU bound source, keep a percpu array of the sink devices. Also, add support for building a path to the CPU local sink from the ETM. This adds a new percpu sink type CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM. This new sink type is exclusively available and can only work with percpu source type device CORESIGHT_DEV_SUBTYPE_SOURCE_PROC. This defines a percpu structure that accommodates a single coresight_device which can be used to store an initialized instance from a sink driver. As these sinks are exclusively linked and dependent on corresponding percpu sources devices, they should also be the default sink device during a perf session. Outwards device connections are scanned while establishing paths between a source and a sink device. But such connections are not present for certain percpu source and sink devices which are exclusively linked and dependent. Build the path directly and skip connection scanning for such devices. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Tested-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Reviewed-by: NMike Leach <mike.leach@linaro.org> Signed-off-by: NAnshuman Khandual <anshuman.khandual@arm.com> [Moved the set/get percpu sink APIs from TRBE patch to here Fixed build break on arm32] Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20210405164307.1720226-17-suzuki.poulose@arm.comSigned-off-by: NMathieu Poirier <mathieu.poirier@linaro.org>
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由 Suzuki K Poulose 提交于
mainline inclusion from mainline-v5.12-rc3 commit 549452b7 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210405164307.1720226-16-suzuki.poulose@arm.com -------------------------------------------------------------------------- The context associated with an ETM for a given perf event includes : - handle -> the perf output handle for the AUX buffer. - the path for the trace components - the buffer config for the sink. The path and the buffer config are part of the "aux_priv" data (etm_event_data) setup by the setup_aux() callback, and made available via perf_get_aux(handle). Now with a sink supporting IRQ, the sink could "end" an output handle when the buffer reaches the programmed limit and would try to restart a handle. This could fail if there is not enough space left the AUX buffer (e.g, the userspace has not consumed the data). This leaves the "handle" disconnected from the "event" and also the "perf_get_aux()" cleared. This all happens within the sink driver, without the etm_perf driver being aware. Now when the event is actually stopped, etm_event_stop() will need to access the "event_data". But since the handle is not valid anymore, we loose the information to stop the "trace" path. So, we need a reliable way to access the etm_event_data even when the handle may not be active. This patch replaces the per_cpu handle array with a per_cpu context for the ETM, which tracks the "handle" as well as the "etm_event_data". The context notes the etm_event_data at etm_event_start() and clears it at etm_event_stop(). This makes sure that we don't access a stale "etm_event_data" as we are guaranteed that it is not freed by free_aux() as long as the event is active and tracing, also provides us with access to the critical information needed to wind up a session even in the absence of an active output_handle. This is not an issue for the legacy sinks as none of them supports an IRQ and is centrally handled by the etm-perf. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Anshuman Khandual <anshuman.khandual@arm.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Reviewed-by: NMike Leach <mike.leach@linaro.org> Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20210405164307.1720226-16-suzuki.poulose@arm.comSigned-off-by: NMathieu Poirier <mathieu.poirier@linaro.org>
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由 Suzuki K Poulose 提交于
mainline inclusion from mainline-v5.12-rc3 commit 35e1c916 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210405164307.1720226-14-suzuki.poulose@arm.com -------------------------------------------------------------------------- Add ETE as one of the supported device types we support with ETM4x driver. The devices are named following the existing convention as ete<N>. ETE mandates that the trace resource status register is programmed before the tracing is turned on. For the moment simply write to it indicating TraceActive. Cc: Mike Leach <mike.leach@linaro.org> Reviewed-by: NMike Leach <mike.leach@linaro.org> Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20210405164307.1720226-14-suzuki.poulose@arm.comSigned-off-by: NMathieu Poirier <mathieu.poirier@linaro.org>
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由 Suzuki K Poulose 提交于
mainline inclusion from mainline-v5.12-rc3 commit 3e666ad0 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210405164307.1720226-13-suzuki.poulose@arm.com -------------------------------------------------------------------------- Add support for handling the system registers for Embedded Trace Extensions (ETE). ETE shares most of the registers with ETMv4 except for some and also adds some new registers. Re-arrange the ETMv4x list to share the common definitions and add the ETE sysreg support. Cc: Mike Leach <mike.leach@linaro.org> Reviewed-by: NMike Leach <mike.leach@linaro.org> Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20210405164307.1720226-13-suzuki.poulose@arm.comSigned-off-by: NMathieu Poirier <mathieu.poirier@linaro.org>
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由 Jonathan Zhou 提交于
mainline inclusion from mainline-v5.11-rc5 commit e5d51fbe category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210110224850.1880240-29-suzuki.poulose@arm.com -------------------------------------------------------------------------- v8.4 tracing extensions added support for trace filtering controlled by TRFCR_ELx. This must be programmed to allow tracing at EL1/EL2 and EL0. The timestamp used is the virtual time. Also enable CONTEXIDR_EL2 tracing if we are running the kernel at EL2. Link: https://lore.kernel.org/r/20210110224850.1880240-29-suzuki.poulose@arm.com Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Will Deacon <will@kernel.org> Reviewed-by: NMathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: NJonathan Zhou <jonathan.zhouwen@huawei.com> [ Move the trace filtering setup etm_init_arch_data() and clean ups] Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: NMathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-31-mathieu.poirier@linaro.orgSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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由 Suzuki K Poulose 提交于
mainline inclusion from mainline-v5.12-rc3 commit 3f9b72f6 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210405164307.1720226-5-suzuki.poulose@arm.com -------------------------------------------------------------------------- This adds TRBE related registers and corresponding feature macros. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Reviewed-by: NMike Leach <mike.leach@linaro.org> Acked-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NAnshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20210405164307.1720226-5-suzuki.poulose@arm.comSigned-off-by: NMathieu Poirier <mathieu.poirier@linaro.org>
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由 Jonathan Zhou 提交于
mainline inclusion from mainline-v5.11-rc5 commit 4b6929f5 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210201181351.1475223-30-mathieu.poirier@linaro.org -------------------------------------------------------------------------- Add definitions for the Arm v8.4 SelfHosted trace extensions registers. [ split the register definitions to separate patch rename some of the symbols ] Link: https://lore.kernel.org/r/20210110224850.1880240-28-suzuki.poulose@arm.com Cc: Will Deacon <will@kernel.org> Acked-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NJonathan Zhou <jonathan.zhouwen@huawei.com> Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: NMathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-30-mathieu.poirier@linaro.orgSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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由 Suzuki K Poulose 提交于
mainline inclusion from mainline-v5.11-rc5 commit 5214b563 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210110224850.1880240-26-suzuki.poulose@arm.com -------------------------------------------------------------------------- Add support for devices with system instruction access only. They don't have a memory mapped interface and thus are not AMBA devices. System register access is not permitted to TRCPDCR and thus skip access to them. Link: https://lore.kernel.org/r/20210110224850.1880240-26-suzuki.poulose@arm.com Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: NMathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-28-mathieu.poirier@linaro.orgSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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由 Suzuki K Poulose 提交于
mainline inclusion from mainline-v5.11-rc5 commit c23bc382 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210110224850.1880240-24-suzuki.poulose@arm.com -------------------------------------------------------------------------- CoreSight ETM with system register access may not have a memory mapped i/o access. Refactor the ETM specific probing into a common routine to allow reusing the code for such ETMs. Link: https://lore.kernel.org/r/20210110224850.1880240-24-suzuki.poulose@arm.com Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: NMathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-26-mathieu.poirier@linaro.orgSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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由 Suzuki K Poulose 提交于
mainline inclusion from mainline-v5.11-rc5 commit 8b94db1e category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210110224850.1880240-20-suzuki.poulose@arm.com -------------------------------------------------------------------------- We have been using TRCIDR1 for detecting the ETM version. This is in preparation for the future IP support. Link: https://lore.kernel.org/r/20210110224850.1880240-20-suzuki.poulose@arm.com Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: NMathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-22-mathieu.poirier@linaro.orgSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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由 Suzuki K Poulose 提交于
mainline inclusion from mainline-v5.11-rc5 commit 1ab3bb9d category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210110224850.1880240-22-suzuki.poulose@arm.com -------------------------------------------------------------------------- As per the specification any update to the TRCPRGCTLR must be synchronized by a context synchronization event (in our case an explicist ISB) before the TRCSTATR is checked. Link: https://lore.kernel.org/r/20210110224850.1880240-22-suzuki.poulose@arm.com Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: NMathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-24-mathieu.poirier@linaro.orgSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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由 Suzuki K Poulose 提交于
mainline inclusion from mainline-v5.11-rc5 commit dc1747a7 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210110224850.1880240-23-suzuki.poulose@arm.com -------------------------------------------------------------------------- ETM v4.4 onwards adds support for system instruction access to the ETM. Detect the support on an ETM and switch to using the mode when available. Link: https://lore.kernel.org/r/20210110224850.1880240-23-suzuki.poulose@arm.com Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: NMathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-25-mathieu.poirier@linaro.orgSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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由 Suzuki K Poulose 提交于
mainline inclusion from mainline-v5.11-rc5 commit fd6e7905 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210110224850.1880240-19-suzuki.poulose@arm.com -------------------------------------------------------------------------- In preparation to detect the support for system instruction support, move the detection of the device access to the target CPU. Link: https://lore.kernel.org/r/20210110224850.1880240-19-suzuki.poulose@arm.com Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: NMathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-21-mathieu.poirier@linaro.orgSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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由 Suzuki K Poulose 提交于
mainline inclusion from mainline-v5.11-rc5 commit e49516e2 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210110224850.1880240-18-suzuki.poulose@arm.com -------------------------------------------------------------------------- We are about to rely on TRCDEVARCH for detecting the ETM and its architecture version, falling back to TRCIDR1 if the former is not implemented (in older broken implementations). Also, we use the architecture version information to make some decisions. Streamline the architecture version handling by adding helpers. Link: https://lore.kernel.org/r/20210110224850.1880240-18-suzuki.poulose@arm.comSigned-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: NMathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-20-mathieu.poirier@linaro.orgSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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由 Suzuki K Poulose 提交于
mainline inclusion from mainline-v5.11-rc5 commit 33d5573a category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210110224850.1880240-15-suzuki.poulose@arm.com -------------------------------------------------------------------------- The Software lock is not implemented for system instructions based accesses. So, skip the lock register access in such cases. Link: https://lore.kernel.org/r/20210110224850.1880240-15-suzuki.poulose@arm.com Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: NMathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-17-mathieu.poirier@linaro.orgSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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由 Suzuki K Poulose 提交于
mainline inclusion from mainline-v5.11-rc5 commit d02dfac3 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210110224850.1880240-14-suzuki.poulose@arm.com -------------------------------------------------------------------------- Define the fields of the DEVARCH register for identifying a component as an ETMv4.x unit. Going forward, we use the DEVARCH register for the component identification, rather than the TRCIDR3. Link: https://lore.kernel.org/r/20210110224850.1880240-14-suzuki.poulose@arm.com Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: NMathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-16-mathieu.poirier@linaro.orgSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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由 Suzuki K Poulose 提交于
mainline inclusion from mainline-v5.11-rc5 commit 91b9f018 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210110224850.1880240-13-suzuki.poulose@arm.com -------------------------------------------------------------------------- Some of the management registers in ETMv4.x are not accessible via system register instructions. Thus we must hide the sysfs files exposing them to the userspace, to prevent system crashes. This patch adds an is_visible() routine to control the visibility at runtime for the registers that may not be accessed. Link: https://lore.kernel.org/r/20210110224850.1880240-13-suzuki.poulose@arm.com Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: NMathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-15-mathieu.poirier@linaro.orgSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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由 Suzuki K Poulose 提交于
mainline inclusion from mainline-v5.11-rc5 commit 03336d0f category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210110224850.1880240-12-suzuki.poulose@arm.com -------------------------------------------------------------------------- ETM architecture defines the system instructions for accessing via register accesses. Add basic support for accessing a given register via system instructions. We split the list of registers as : 1) Accessible only from memory mapped interface 2) Accessible from system register instructions. All registers are accessible via the memory-mapped interface. However, some registers are not accessible via the system instructions. This list is then used to further filter out the files we expose via sysfs. Link: https://lore.kernel.org/r/20210110224850.1880240-12-suzuki.poulose@arm.com Cc: Mike Leach <mike.leach@linaro.org> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: NMathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-14-mathieu.poirier@linaro.orgSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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由 Suzuki K Poulose 提交于
mainline inclusion from mainline-v5.11-rc5 commit c03ceec1 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210110224850.1880240-10-suzuki.poulose@arm.com -------------------------------------------------------------------------- Some of the ETM management registers are not accessible via system instructions. Thus we need to filter accesses to these registers depending on the access mechanism for the ETM at runtime. The driver can cope with this for normal operation, by regular checks. But the driver also exposes them via sysfs, which now needs to be removed. So far, we have used the generic coresight sysfs helper macros to export a given device register, defining a "show" operation per register. This is not helpful to filter the files at runtime, based on the access. In order to do this dynamically, we need to filter the attributes by offsets and hard coded "show" functions doesn't make this easy. Thus, switch to extended attributes, storing the offset in the scratch space. This allows us to implement filtering based on the offset and also saves us some text size. This will be later used for determining a given attribute must be "visible" via sysfs. Link: https://lore.kernel.org/r/20210110224850.1880240-10-suzuki.poulose@arm.com Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: NMathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-12-mathieu.poirier@linaro.orgSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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由 Suzuki K Poulose 提交于
mainline inclusion from mainline-v5.11-rc5 commit 5e2acf9d category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210110224850.1880240-8-suzuki.poulose@arm.com -------------------------------------------------------------------------- As we are about to add support for sysreg access to ETM4.4+ components, make sure that we read the registers only on the host CPU. Link: https://lore.kernel.org/r/20210110224850.1880240-8-suzuki.poulose@arm.com Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: NMathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-10-mathieu.poirier@linaro.orgSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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由 Suzuki K Poulose 提交于
mainline inclusion from mainline-v5.11-rc5 commit 8ce00296 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210110224850.1880240-7-suzuki.poulose@arm.com -------------------------------------------------------------------------- Convert the generic CLAIM tag management APIs to use the device access layer abstraction. Link: https://lore.kernel.org/r/20210110224850.1880240-7-suzuki.poulose@arm.com Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: NMathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-9-mathieu.poirier@linaro.orgSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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由 Suzuki K Poulose 提交于
mainline inclusion from mainline-v5.11-rc5 commit 02005282 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210110224850.1880240-6-suzuki.poulose@arm.com -------------------------------------------------------------------------- Convert the generic routines to use the new access abstraction layer gradually, starting with coresigth_timeout. Link: https://lore.kernel.org/r/20210110224850.1880240-6-suzuki.poulose@arm.com Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: NMathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-8-mathieu.poirier@linaro.orgSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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由 Suzuki K Poulose 提交于
mainline inclusion from mainline-v5.11-rc5 commit 6e736c60 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210110224850.1880240-4-suzuki.poulose@arm.com -------------------------------------------------------------------------- We are about to introduce support for sysreg access to ETMv4.4+ component. Since there are generic routines that access the registers (e.g, CS_LOCK/UNLOCK , claim/disclaim operations, timeout) and in order to preserve the logic of these operations at a single place we introduce an abstraction layer for the accesses to a given device. Link: https://lore.kernel.org/r/20210110224850.1880240-4-suzuki.poulose@arm.com Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: NMathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-6-mathieu.poirier@linaro.orgSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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- 22 11月, 2022 1 次提交
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由 openeuler-ci-bot 提交于
Merge Pull Request from: @allen-shi This is a cherry-pick of [PR82](https://gitee.com/openeuler/kernel/pulls/82) and [PR120](https://gitee.com/openeuler/kernel/pulls/120) from openEuler-22.09 branch. [PR120](https://gitee.com/openeuler/kernel/pulls/120) is to fix the issue for [PR82](https://gitee.com/openeuler/kernel/pulls/82). ### For [PR82](https://gitee.com/openeuler/kernel/pulls/82), the patch set is to add uncore PMU support for Intel Sapphire Rapids platform. It includes generic uncore discovery support and SPR specific uncore event support. Generic uncore discovery support contains: a) Feature patches from upstream 5.13-rc1(5 commits): c4c55e36 perf/x86/intel/uncore: Generic support for the MMIO type of uncore blocks 42839ef4 perf/x86/intel/uncore: Generic support for the PCI type of uncore blocks 6477dc39 perf/x86/intel/uncore: Rename uncore_notifier to uncore_pci_sub_notifier d6c75413 perf/x86/intel/uncore: Generic support for the MSR type of uncore blocks edae1f06 perf/x86/intel/uncore: Parse uncore discovery tables b) To fix rb_find/rb_add implicit declaration errors, adding rbtree helper patches(v5.12-rc1, 7 commits): 798172b1 rbtree, timerqueue: Use rb_add_cached() 5a798725 rbtree, rtmutex: Use rb_add_cached() a905e84e rbtree, uprobes: Use rbtree helpers a3b89864 rbtree, perf: Use new rbtree helpers 8ecca394 rbtree, sched/deadline: Use rb_add_cached() bf9be9a1 rbtree, sched/fair: Use rb_add_cached() 2d24dd57 rbtree: Add generic add and find helpers c) To fix error(too few arguments to function ‘uncore_pci_pmu_register’), add dependent patches(5.12-rc1, 2): 9a7832ce perf/x86/intel/uncore: With > 8 nodes, get pci bus die id from NUMA info ba9506be perf/x86/intel/uncore: Store the logical die id instead of the physical die id. SPR platform specific uncore support contains: a) Feature upstream patches from mainline v5.15-rc1(15 commits): c76826a6 perf/x86/intel/uncore: Support IMC free-running counters on Sapphire Rapids server 0378c93a perf/x86/intel/uncore: Support IIO free-running counters on Sapphire Rapids server 1583971b perf/x86/intel/uncore: Factor out snr_uncore_mmio_map() 8053f2d7 perf/x86/intel/uncore: Add alias PMU name 0d771caf perf/x86/intel/uncore: Add Sapphire Rapids server MDF support 2a8e51ea perf/x86/intel/uncore: Add Sapphire Rapids server M3UPI support da5a9156 perf/x86/intel/uncore: Add Sapphire Rapids server UPI support f57191ed perf/x86/intel/uncore: Add Sapphire Rapids server M2M support 85f2e30f perf/x86/intel/uncore: Add Sapphire Rapids server IMC support 0654dfdc perf/x86/intel/uncore: Add Sapphire Rapids server PCU support f85ef898 perf/x86/intel/uncore: Add Sapphire Rapids server M2PCIe support e199eb51 perf/x86/intel/uncore: Add Sapphire Rapids server IRP support 3ba7095b perf/x86/intel/uncore: Add Sapphire Rapids server IIO support 949b1138 perf/x86/intel/uncore: Add Sapphire Rapids server CHA support c54c53d9 perf/x86/intel/uncore: Add Sapphire Rapids server framework b) Two SPR model name related changes to make above patches apply cleanly(2 commits): (5.14-rc2) 28188cc4 x86/cpu: Fix core name for Sapphire Rapids (5.13-rc1) 53375a5a x86/cpu: Resort and comment Intel models c) Some SPR uncore related bugfixes(6 commits): v5.16-rc1: 4034fb20 perf/x86/intel/uncore: Fix Intel SPR M3UPI event constraints f01d7d55 perf/x86/intel/uncore: Fix Intel SPR M2PCIE event constraints 67c5d443 perf/x86/intel/uncore: Fix Intel SPR IIO event constraints 9d756e40 perf/x86/intel/uncore: Fix Intel SPR CHA event constraints e2bb9fab perf/x86/intel/uncore: Fix invalid unit check v5.13-rc6: 4a0e3ff3 perf/x86/intel/uncore: Fix a kernel WARNING triggered by maxcpus=1 **Intel-kernel issue:** [#I5BECO](https://gitee.com/openeuler/intel-kernel/issues/I5BECO) **Test:** With this patch set, on SPR: ``` # cat /sys/devices/uncore_cha_1/alias uncore_type_0_1 # perf stat -a -e uncore_imc_0/event=0x1/ -- sleep 1 Performance counter stats for 'system wide': 2,407,096,566 uncore_imc_0/event=0x1/ 1.002850766 seconds time elapsed # perf stat -a -e uncore_imc_free_running_0/rpq_cycles/ -- sleep 1 Performance counter stats for 'system wide': 13,879,446 uncore_imc_free_running_0/rpq_cycles/ 1.002852701 seconds time elapsed ``` Without this patch set, the "uncore_cha_1" like devices are not available under /sys/devices, and the above like uncore events will be "not supported". **Known issue:** N/A **Default config change:** N/A ### For [PR120](https://gitee.com/openeuler/kernel/pulls/120), it is to cherry-pick upstream fix for commit c6bc9bd06dff ("rbtree, uprobes: Use rbtree helpers") **BPFTrace Issue** [#I5RUM5](https://gitee.com/src-openeuler/bpftrace/issues/I5RUM5) **Tests** 1, run bpftrace /usr/share/bpftrace/tools/bashreadline.bt without the fix, we can see the core dump 2, Apply the fix, and run bpftrace /usr/share/bpftrace/tools/bashreadline.bt, the issue disappears. **Known Issue** N/A **Default config change** N/A Link:https://gitee.com/openeuler/kernel/pulls/229 Reviewed-by: Jun Tian <jun.j.tian@intel.com> Reviewed-by: Zheng Zengkai <zhengzengkai@huawei.com> Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
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