1. 30 5月, 2014 5 次提交
    • J
      MIPS: KVM: Move KVM_{GET,SET}_ONE_REG definitions into kvm_host.h · 48a3c4e4
      James Hogan 提交于
      Move the KVM_{GET,SET}_ONE_REG MIPS register id definitions out of
      kvm_mips.c to kvm_host.h so that they can be shared between multiple
      source files. This allows register access to be indirected depending on
      the underlying implementation (trap & emulate or VZ).
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: kvm@vger.kernel.org
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: David Daney <david.daney@cavium.com>
      Cc: Sanjay Lal <sanjayl@kymasys.com>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      48a3c4e4
    • J
      MIPS: KVM: Add CP0_EPC KVM register access · fb6df0cd
      James Hogan 提交于
      Contrary to the comment, the guest CP0_EPC register cannot be set via
      kvm_regs, since it is distinct from the guest PC. Add the EPC register
      to the KVM_{GET,SET}_ONE_REG ioctl interface.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: kvm@vger.kernel.org
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: David Daney <david.daney@cavium.com>
      Cc: Sanjay Lal <sanjayl@kymasys.com>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      fb6df0cd
    • J
      MIPS: KVM: Use local_flush_icache_range to fix RI on XBurst · facaaec1
      James Hogan 提交于
      MIPS KVM uses mips32_SyncICache to synchronise the icache with the
      dcache after dynamically modifying guest instructions or writing guest
      exception vector. However this uses rdhwr to get the SYNCI step, which
      causes a reserved instruction exception on Ingenic XBurst cores.
      
      It would seem to make more sense to use local_flush_icache_range()
      instead which does the same thing but is more portable.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: kvm@vger.kernel.org
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: Sanjay Lal <sanjayl@kymasys.com>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      facaaec1
    • J
      MIPS: KVM: Allocate at least 16KB for exception handlers · 7006e2df
      James Hogan 提交于
      Each MIPS KVM guest has its own copy of the KVM exception vector. This
      contains the TLB refill exception handler at offset 0x000, the general
      exception handler at offset 0x180, and interrupt exception handlers at
      offset 0x200 in case Cause_IV=1. A common handler is copied to offset
      0x2000 and offset 0x3000 is used for temporarily storing k1 during entry
      from guest.
      
      However the amount of memory allocated for this purpose is calculated as
      0x200 rounded up to the next page boundary, which is insufficient if 4KB
      pages are in use. This can lead to the common handler at offset 0x2000
      being overwritten and infinitely recursive exceptions on the next exit
      from the guest.
      
      Increase the minimum size from 0x200 to 0x4000 to cover the full use of
      the page.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: kvm@vger.kernel.org
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: Sanjay Lal <sanjayl@kymasys.com>
      Cc: stable@vger.kernel.org
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      7006e2df
    • D
      MIPS: KVM: remove the stale memory alias support function unalias_gfn · 356d4c20
      Deng-Cheng Zhu 提交于
      The memory alias support has been removed since a1f4d395 (KVM: Remove
      memory alias support). So remove unalias_gfn from the MIPS port.
      Reviewed-by: NJames Hogan <james.hogan@imgtec.com>
      Signed-off-by: NDeng-Cheng Zhu <dengcheng.zhu@imgtec.com>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      356d4c20
  2. 25 1月, 2014 1 次提交
    • J
      MIPS: KVM: remove shadow_tlb code · 08596b0a
      James Hogan 提交于
      The kvm_mips_init_shadow_tlb() function is called from
      kvm_arch_vcpu_init() and initialises entries 0 to
      current_cpu_data.tlbsize-1 of the virtual cpu's shadow_tlb[64] array.
      
      However newer cores with FTLBs can have a tlbsize > 64, for example the
      ProAptiv I'm testing on has a total tlbsize of 576. This causes
      kvm_mips_init_shadow_tlb() to overflow the shadow_tlb[64] array and
      overwrite the comparecount_timer among other things, causing a lock up
      when starting a KVM guest.
      
      Aside from kvm_mips_init_shadow_tlb() which only initialises it, the
      shadow_tlb[64] array is only actually used by the following functions:
       - kvm_shadow_tlb_put() & kvm_shadow_tlb_load()
           These are never called. The only call sites are #if 0'd out.
       - kvm_mips_dump_shadow_tlbs()
           This is never called.
      
      It was originally added for trap & emulate, but turned out to be
      unnecessary so it was disabled.
      
      So instead of fixing the shadow_tlb initialisation code, lets just
      remove the shadow_tlb[64] array and the above functions entirely. The
      only functional change here is the removal of broken shadow_tlb
      initialisation. The rest just deletes dead code.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: Gleb Natapov <gleb@redhat.com>
      Cc: kvm@vger.kernel.org
      Cc: Sanjay Lal <sanjayl@kymasys.com>
      Acked-by: NPaolo Bonzini <pbonzini@redhat.com>
      Signed-off-by: NJohn Crispin <blogic@openwrt.org>
      Patchwork: http://patchwork.linux-mips.org/patch/6384/
      08596b0a
  3. 17 10月, 2013 1 次提交
  4. 18 7月, 2013 1 次提交
  5. 11 6月, 2013 1 次提交
  6. 03 6月, 2013 4 次提交
  7. 08 5月, 2013 1 次提交