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  1. 13 7月, 2019 1 次提交
  3. 18 6月, 2019 1 次提交
    • A
      clk: imx6q: fix section mismatch warning · 0e12248c
      由 Arnd Bergmann 提交于 
      The imx6q_obtain_fixed_clk_hw lacks an __init marker, which
leads to this otherwise harmless warning:

WARNING: vmlinux.o(.text+0x495358): Section mismatch in reference from the function imx6q_obtain_fixed_clk_hw() to the function .init.text:imx_obtain_fixed_clock_hw()
The function imx6q_obtain_fixed_clk_hw() references
the function __init imx_obtain_fixed_clock_hw().
This is often because imx6q_obtain_fixed_clk_hw lacks a __init
annotation or the annotation of imx_obtain_fixed_clock_hw is wrong.

Fixes: 992b703b ("clk: imx6q: Switch to clk_hw based API")
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>
      0e12248c
  5. 07 6月, 2019 2 次提交
  7. 23 5月, 2019 1 次提交
  9. 29 12月, 2018 1 次提交
  11. 11 12月, 2018 4 次提交
    • L
      clk: imx6q: handle ENET PLL bypass · 3cc48976
      由 Lucas Stach 提交于 
      The ENET PLL is different from the other i.MX6 PLLs, as it has
multiple outputs with different post-dividers, which are all
bypassed if the single bypass bit is activated. The hardware setup
looks something like this:
                                _
refclk-o---PLL---o----DIV1-----| \
       |         |             |M |----OUT1
       o-----------------------|_/
       |         |              _
       |         o----DIV2-----| \
       |         |             |M |----OUT2
       o-----------------------|_/
       |         |              _
       |         `----DIV3-----| \
       |                       |M |----OUT3
       `-----------------------|_/

The bypass bit not only bypasses the PLL, but also the attached
post-dividers. This would be reasonbly straight forward to model
with a single output, or with different bypass bits for each output,
but sadly the HW guys decided that it would be good to actuate all
3 muxes with a single bit.

So the need to have the PLL bypassed for one of the outputs always
affects 2 other (in our model) independent branches of the clock
tree.

This means the decision to bypass this PLL is a system wide design
choice and should not be changed on-the-fly, so we can treat any
bapass configuration as static. As such we can just register the
post-dividiers with a ratio that reflects the bypass status, which
allows us to bypass the PLL without breaking our abstraction model
and with it DT stability.
Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>
      3cc48976
    • L
      clk: imx6q: optionally get CCM inputs via standard clock handles · a29be918
      由 Lucas Stach 提交于 
      When specifying external clock inputs to the CCM the current code
requires the clocks to be in a "clocks" child node of the DT root.
This is not really conformant with DT best practices.

To avoid the need to deviate from those best practices, allow the
clock inputs to be specified via standard clock handles. This is
in line with how drivers of the later CCM driver revisions on
newer i.MX SoCs handle this.

As we can't retroactively change the DT binding, allow this as an
option with a fallback to the old way of how this has been handled.
Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
Acked-by: NRob Herring <robh@kernel.org>
Reviewed-by: NDong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>
      a29be918
    • L
      clk: imx6q: reset exclusive gates on init · f7542d81
      由 Lucas Stach 提交于 
      The exclusive gates may be set up in the wrong way by software running
before the clock driver comes up. In that case the exclusive setup is
locked in its initial state, as the complementary function can't be
activated without disabling the initial setup first.

To avoid this lock situation, reset the exclusive gates to the off
state and allow the kernel to provide the proper setup.
Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
Reviewed-by: NDong Aisheng <Aisheng.dong@nxp.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>
      f7542d81
    • A
      clk: imx6q: add DCICx clocks gate · 92991494
      由 Anson Huang 提交于 
      On i.MX6QP/i.MX6Q/i.MX6DL, there are DCIC1/DCIC2 clocks
gate in CCM_CCGR0 register, add them into clock tree for
clock management.
Signed-off-by: NAnson Huang <Anson.Huang@nxp.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>
      92991494
  13. 18 10月, 2018 1 次提交
  15. 30 6月, 2018 2 次提交
  17. 02 6月, 2018 1 次提交
  19. 02 11月, 2017 1 次提交
    • S
      clk: imx6: refine hdmi_isfr's parent to make HDMI work on i.MX6 SoCs w/o VPU · c68ee58d
      由 Sébastien Szymanski 提交于 
      On i.MX6 SoCs without VPU (in my case MCIMX6D4AVT10AC), the hdmi driver
fails to probe:

[    2.540030] dwhdmi-imx 120000.hdmi: Unsupported HDMI controller
(0000:00:00)
[    2.548199] imx-drm display-subsystem: failed to bind 120000.hdmi
(ops dw_hdmi_imx_ops): -19
[    2.557403] imx-drm display-subsystem: master bind failed: -19

That's because hdmi_isfr's parent, video_27m, is not correctly ungated.
As explained in commit 5ccc248c ("ARM: imx6q: clk: Add support for
mipi_core_cfg clock as a shared clock gate"), video_27m is gated by
CCM_CCGR3[CG8].

On i.MX6 SoCs with VPU, the hdmi is working thanks to the
CCM_CMEOR[mod_en_ov_vpu] bit which makes the video_27m ungated whatever
is in CCM_CCGR3[CG8]. The issue can be reproduced by setting
CCMEOR[mod_en_ov_vpu] to 0.

Make the HDMI work in every case by setting hdmi_isfr's parent to
mipi_core_cfg.
Signed-off-by: NSébastien Szymanski <sebastien.szymanski@armadeus.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
      c68ee58d
  21. 21 1月, 2017 1 次提交
  23. 01 11月, 2016 3 次提交
  25. 21 9月, 2016 2 次提交
  27. 12 6月, 2016 1 次提交
    • D
      clk: imx: fix pll clock parents · f83d3163
      由 Dong Aisheng 提交于 
      pllx_bypass_src mux shouldn't be the parent of pllx clock
since it's only valid when when pllx BYPASS bit is set.
Thus it is actually one parent of pllx_bypass only.

Instead, pllx parent should be fixed to osc according to
reference manual.
Other plls have the same issue.

e.g. before fix, the pll tree is:
osc                                      6            6    24000000          0 0
   pll1_bypass_src                       0            0    24000000          0 0
      pll1                               0            0   792000000          0 0
         pll1_bypass                     0            0   792000000          0 0
            pll1_sys                     0            0   792000000          0 0

After the fix, it's:
osc                                      6            6    24000000          0 0
   pll1                                  0            0   792000000          0 0
      pll1_bypass                        0            0   792000000          0 0
         pll1_sys                        0            0   792000000          0 0
Signed-off-by: NDong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>
      f83d3163
  29. 13 4月, 2016 1 次提交
  31. 14 2月, 2016 1 次提交
    • B
      clk: imx: Add clock support for imx6qp · ee360274
      由 Bai Ping 提交于 
      most of the clock tree structures on i.MX6 Quad Plus are
same as on i.MX6Q. there still some differences between
these two SOCs. compared to the i.XM6Q, the differents of
clocks on i.MX6QP is mainly on:

1. New clock gate added to support the PRE and PRG modules
2. 24MHz OSC clock option added to the UART, IPG, ECSPI, and
   CAN clock roots.
3. MMDC channel 1 clock gate is now controllable.
4. clock gating added to the LDB_DIx_IPU clocks on i.MX6QP
5. EMI clock root divider fix
6. other updates fo CSCMRx, CSCDRx and CS2CDR registers.

detailed infomation, please refer to the i.MX6QP RM.
Signed-off-by: NBai Ping <ping.bai@nxp.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>
      ee360274
  33. 25 11月, 2015 1 次提交
  35. 12 10月, 2015 1 次提交
    • S
      clk: imx6: Add SPDIF_GCLK clock in clock tree · 84a87250
      由 Shengjiu Wang 提交于 
      Correct SPDIF clock setting issue in clock tree, the SPDIF_GCLK is also
one clock of SPDIF, which is missed before.

We found an issue that imx can't enter low power mode with spdif
if IMX6x_CLK_SPDIF is used as the core clock of spdif. Because
spdif driver will register IMX6x_CLK_SPDIF clock to regmap, regmap will do
clk_prepare in init function, then IMX6x_CLK_SPDIF clock is prepared in probe,
so its parent clock (PLL clock) is prepared, the prepare operation of
PLL clock is to enable the clock. But I.MX needs all PLL clock is disabled,
then it can enter low power mode.

So we can't use IMX6x_CLK_SPDIF as the core clock of spdif, the correct spdif
core clock is SPDIF_GCLK, which share same gate bit with IMX6x_CLK_SPDIF clock.
SPDIF_GCLK's parent clock is ipg clock.
Signed-off-by: NShengjiu Wang <shengjiu.wang@freescale.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>
      84a87250
  37. 26 9月, 2015 1 次提交
  39. 10 8月, 2015 1 次提交
  41. 13 7月, 2015 1 次提交
  43. 03 6月, 2015 6 次提交
  45. 02 3月, 2015 5 次提交