It is require to dispose all virtual irq of hwirq on chip
created on given irq domain before removing this irq domain.
Hence dispose all mapped irqs before deleting the irq domains
in regmap_del_irq_chip();
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Tested-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Some of devices supports the trigger level for interrupt
like rising/falling edge specially for GPIOs. The interrupt
support of such devices may have uses the generic regmap irq
framework for implementation.

Add support to configure the trigger type device interrupt
register via regmap-irq framework. The regmap-irq framework
configures the trigger register only if the details of trigger
type registers are provided.

[Fixed use of terery operator for legibility -- broonie]
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Replace kmalloc with specialized function kmalloc_array when the size
is a multiplication of : number * size
Signed-off-by: Nlixiubo <lixiubo@cmss.chinamobile.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Replace kzalloc with specialized function kcalloc when the size is
a multiplication of : number * sizeof
Signed-off-by: Nlixiubo <lixiubo@cmss.chinamobile.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

An user will be CSR SiRFSoC ARM chips.
Signed-off-by: NGuo Zeng <Guo.Zeng@csr.com>
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Some chips have separate unmask registers from mask registers for
some consideration of concurrency SMP write performance. And this
patch adds a flag for it.

An user will be CSR SiRFSoC ARM chips.
Signed-off-by: NGuo Zeng <Guo.Zeng@csr.com>
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

use_single_rw currently reflects the capabilities of the connected
device. The capabilities of the bus are currently missing for this
variable.

As there are read only and write only buses we need seperate values for
use_single_rw to also reflect tha capabilities of the bus.

This patch splits use_single_rw into use_single_read and
use_single_write. The initialization is changed to check the
configuration for use_single_rw and to check the capabilities of the
used bus.
Signed-off-by: NMarkus Pargmann <mpa@pengutronix.de>
Signed-off-by: NMark Brown <broonie@kernel.org>

set_irq_flags is ARM specific with custom flags which have genirq
equivalents. Convert drivers to use the genirq interfaces directly, so we
can kill off set_irq_flags. The translation of flags is as follows:

IRQF_VALID -> !IRQ_NOREQUEST
IRQF_PROBE -> !IRQ_NOPROBE
IRQF_NOAUTOEN -> IRQ_NOAUTOEN

For IRQs managed by an irqdomain, the irqdomain core code handles clearing
and setting IRQ_NOREQUEST already, so there is no need to do this in
.map() functions and we can simply remove the set_irq_flags calls. Some
users also set IRQ_NOPROBE and this has been maintained although it is not
clear that is really needed. There appears to be a great deal of blind
copy and paste of this code.
Signed-off-by: NRob Herring <robh@kernel.org>
Signed-off-by: NMark Brown <broonie@kernel.org>

Fixed a typo error in the file
Signed-off-by: NSriram Dash <dash.sriram@gmail.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

The irq_domain_ops are not modified by the driver and the irqdomain core
code accepts pointer to a const data.
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski.k@gmail.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Since commit 1c6c6952 ("genirq: Reject
bogus threaded irq requests") threaded IRQs without a primary handler
need to be requested with IRQF_ONESHOT, otherwise the request will fail.

The %irq_flags flag is used to request the threaded IRQ and is also a
parameter of the caller.  Hence, we cannot be sure that IRQF_ONESHOT is
set.  This change avoids the potentially missing flag by setting
IRQF_ONESHOT when requesting the threaded IRQ.

Generated by: scripts/coccinelle/misc/irqf_oneshot.cocci
Signed-off-by: NValentin Rothberg <Valentin.Rothberg@lip6.fr>
Signed-off-by: NMark Brown <broonie@kernel.org>

Since we cannot make sure the 'chip->num_regs' will always be none zero
from the users, and then if 'chip->num_regs' equals to zero by mistake
or other reasons, the kzalloc() will return ZERO_SIZE_PTR, which equals
to ((void *)16).

So this patch fix this with just checking the 'chip->num_regs' before
calling kzalloc().

This also sorts the header files in alphabetical order at the same time.
Signed-off-by: NXiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: NMark Brown <broonie@linaro.org>

After setting the 'data' pointer (wchich is returned to the caller for
freeing later) the regmap_add_irq_chip() could still fail for various
reasons (ENOMEM, regmap_read or regmap_write failure). In such case the
memory under 'data' was freed in error path and error value was returned
but the 'data' variable was not changed.

This could lead to errors if the caller passed such 'data' to
regmap_del_irq_chip().

The 'data' pointer should be changed atomically from the caller
perspective - set it only on regmap_add_irq_chip() success.
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NMark Brown <broonie@linaro.org>

irqdomain now supports removal of domains on exit so we can properly clean
up on deletion of a regmap irqchip.
Signed-off-by: NMark Brown <broonie@linaro.org>

In some cases, clear interrupt register may be at address 0.
This patch allows to use such configurations by adding additional
configuration bit to indicate this.

[With doc fix from Levente Kurusa <levex@linux.com> -- broonie]
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NMark Brown <broonie@linaro.org>

clear the status bit if the mask register doesn't prevent
the chip level irq from being asserted

OR in the following sequence, there will be irq storm happens:
1) interrupt is triggered;
2) another thread disables it(the mask bit is set);
3) _Then_ the interrupt thread is not ACKed(the status bit is not cleared),
   and it's ignored;
4) if the irq is still asserted because of the uncleared status bit,
   the irq storm happens;
Signed-off-by: NYi Zhang <yizhang@marvell.com>
Signed-off-by: NMark Brown <broonie@linaro.org>

In case the hardware interrupt mask register does not prevent the chip level
irq from being asserted by the corresponding interrupt status bit, already
set interrupt bits should to be cleared once after masking them during
initialization. Add a flag to let drivers enable this behavior.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NMark Brown <broonie@linaro.org>

Display the name for the chip rather than just the primary IRQ so it is
clearer what exactly has failed.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

Even in failed case of pm_runtime_get_sync, the usage_count
is incremented. In order to keep the usage_count with correct
value and runtime power management to behave correctly, call
pm_runtime_put(_sync) in such case.

Signed-off-by Liu Chuansheng <chuansheng.liu@intel.com>
Signed-off-by: NLi Fei <fei.li@intel.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

Support devices which have an enable rather than mask register for wake
sources.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

This wasn't implemented but happened to work on test systems due to lack
of wake mask inversion support.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

If the interrupt status registers are a single block of registers and the
chip supports bulk reads then do a single bulk read rather than pay the
extra I/O cost. This restores the original behaviour which was lost when
support for register striding was added.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

In preparation for adding back support for block reads.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

regmap-irq framework is used vastly by mfd drivers and some of
devices like TPS65910, TPS80036 do not support the wake base
register to enable wake.

Currently wake in regmap-irq only supported if client driver
passes the wake base register.

As the regmap-irq is mostly used by mfd devices and it is require
to have wake support from these devices in most of use cases,
enabling wake support by default in regmap-irq.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

This is useful for integration with other subsystems, especially MFD,
and provides an alternative API for users that request their own IRQs.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

The primary handler will NOT be called if the interrupt nests into
another interrupt thread. Remove it to avoid confusing.
Signed-off-by: NYunfan Zhang <yfzhang@marvell.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

Currently, regmap will write 1 to mask_base to mask
an interrupt and write 0 to unmask it.

But some chips do not have an interrupt mask register,
and only have interrupt enable register.
Then we should write 0 to disable interrupt and 1 to enable.

So add an mask_invert flag to handle this.
If it is not set, behavior is same as previous.
If set it to 1, the mask value will be inverted
before written to mask_base
Signed-off-by: NXiaofan Tian <tianxf@marvell.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

Some devices need to have a runtime PM reference while handling interrupts
to ensure that the register I/O is available. Support this with a flag in
the chip.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

The kerneldoc for irq_set_irq_wake() says:

    Enable/disable power management wakeup mode, which is
    disabled by default.

regmap_irq_set_wake() clears bits to enable wake for an interrupt,
and sets bits to disable wake. Hence, we should set all bits in
wake_buf initially, to mirror the expected disabled state.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

If a regmap-irq chip has no wake base:

* There's no point calling .irq_set_wake, hence IRQCHIP_SKIP_SET_WAKE.

* If some IRQs in the chip are enabled for wake and some aren't, we
  should mask those interrupts that are not wake enabled, so that if
  they occur during suspend, the system is not awoken. Hence,
  IRQCHIP_MASK_ON_SUSPEND.

Note that IRQCHIP_MASK_ON_SUSPEND is handled by check_wakeup_irqs(),
which always iterates over every single interrupt in the system,
irrespective of whether an interrupt is a child of a controller whose
output interrupt has no wake-enabled inputs and hence is presumably
masked itself. Hence this change might cause interrupt unnecessary
masking operations and associated register I/O.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

This is intended to give each irq_chip a useful name, rather than hard-
coding them all as "regmap".
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

This will allow later patches to adjust portions of the irq_chip
individually for each regmap_irq_chip that is created.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

Don't write the full register, it's possible there's bits other than the
masks in the same register which we shouldn't be changing.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Tested-by: NStephen Warren <swarren@wwwdotorg.org>

A number of places in the code were printing error messages that included
the address of a register, but were not calculating the register address
in the same way as the access to the register. Use a temporary to solve
this.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

Allow chips to provide a bank of registers for controlling the wake state
in a similar fashion to the masks and propagate the wake count to the
parent interrupt controller.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

If the driver supplied an empty entry in the array of IRQs then return
an error rather than trying to do the mapping. This is intended for use
with handling chip variants and similar situations.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

We should never be modifying it and it lets drivers declare it const.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

In some chips the IRQ status registers are not contiguous in the register
map but spaced at even spaces. This is an easy case to handle with minor
changes. It is assume for this purpose that the stride for status is
equal to the stride for mask/ack registers as well.
Signed-off-by: NGraeme Gregory <gg@slimlogic.co.uk>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

This gets us up to date with the recommended current kernel infrastructure
and should transparently give us device tree interrupt bindings for any
devices using the framework. If an explicit IRQ mapping is passed in then
a legacy interrupt range is created, otherwise a simple linear mapping is
used. Previously a mapping was mandatory so existing drivers should not
be affected.

A function regmap_irq_get_virq() is provided to allow drivers to map
individual IRQs which should be used in preference to the existing
regmap_irq_chip_get_base() which is only valid if a legacy IRQ range is
provided.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>