- 23 1月, 2012 1 次提交
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由 Russell King 提交于
Add a new seqfile for reporting coherent DMA allocations. This contains the address range, size and the function which was used to allocate each region, allowing these allocations to be viewed in much the same way as /proc/vmallocinfo. The DMA coherent region has limited space, so this allows allocation failures to be viewed, as well as finding out how much space is being used. Make sure this file is only readable by root - same as vmallocinfo - to prevent information leakage. Acked-by: NNicolas Pitre <nico@linaro.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 13 1月, 2012 1 次提交
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由 Russell King 提交于
Several platforms are now using the memblock_alloc+memblock_free+ memblock_remove trick to obtain memory which won't be mapped in the kernel's page tables. Most platforms do this (correctly) in the ->reserve callback. However, OMAP has started to call these functions outside of this callback, and this is extremely unsafe - memory will not be unmapped, and could well be given out after memblock is no longer responsible for its management. So, provide arm_memblock_steal() to perform this function, and ensure that it panic()s if it is used inappropriately. Convert everyone over, including OMAP. As a result, OMAP with OMAP4_ERRATA_I688 enabled will panic on boot with this change. Mark this option as BROKEN and make it depend on BROKEN. OMAP needs to be fixed, or 137d105d (ARM: OMAP4: Fix errata i688 with MPU interconnect barriers.) reverted until such time it can be fixed correctly. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 24 12月, 2011 1 次提交
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由 Dave Martin 提交于
Activation conditions for a workaround should not be encoded in the workaround's direct dependencies if this makes otherwise reasonable configuration choices impossible. This patches uses the SMP/UP patching facilities instead to compile out the workaround if the configuration means that it is definitely not needed. This means that configs for buggy silicon can simply select ARM_ERRATA_751472, without preventing a UP kernel from being built or duplicatiing knowledge about when to activate the workaround. This seems the correct way to do things, because the erratum is a property of the silicon, irrespective of what the kernel config happens to be. Signed-off-by: NDave Martin <dave.martin@linaro.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 19 12月, 2011 1 次提交
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由 Dave Martin 提交于
Making CACHE_L2X0 depend on (huge list of MACH_ and ARCH_ configs) is bothersome to maintain and likely to lead to merge conflicts. This patch moves the knowledge of which platforms have a L2x0 or PL310 cache controller to the individual machines. To enable this, a new MIGHT_HAVE_CACHE_L2X0 config option is introduced to allow machines to indicate that they may have such a cache controller independently of each other. Boards/SoCs which cannot reliably operate without the L2 cache controller support will need to select CACHE_L2X0 directly from their own Kconfigs instead. This applies to some TrustZone-enabled boards where Linux runs in the Normal World, for example. Signed-off-by: NDave Martin <dave.martin@linaro.org> Acked-by: NAnton Vorontsov <cbouatmailru@gmail.com> (for cns3xxx) Acked-by: NTony Lindgren <tony@atomide.com> (for omap) Acked-by: NShawn Guo <shawn.guo@linaro.org> (for imx) Acked-by: NKukjin Kim <kgene.kim@samsung.com> (for exynos) Acked-by: NSascha Hauer <s.hauer@pengutronix.de> (for imx) Acked-by: NOlof Johansson <olof@lixom.net> (for tegra)
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- 11 12月, 2011 1 次提交
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由 Pawel Moll 提交于
This patch adds processor info for ARM Ltd. Cortex-A7. A7 is architecturally identical to A15 so it shares the same SMP initialization code and hwcaps. Tested-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NPawel Moll <pawel.moll@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 09 12月, 2011 3 次提交
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由 Tejun Heo 提交于
The only function of memblock_analyze() is now allowing resize of memblock region arrays. Rename it to memblock_allow_resize() and update its users. * The following users remain the same other than renaming. arm/mm/init.c::arm_memblock_init() microblaze/kernel/prom.c::early_init_devtree() powerpc/kernel/prom.c::early_init_devtree() openrisc/kernel/prom.c::early_init_devtree() sh/mm/init.c::paging_init() sparc/mm/init_64.c::paging_init() unicore32/mm/init.c::uc32_memblock_init() * In the following users, analyze was used to update total size which is no longer necessary. powerpc/kernel/machine_kexec.c::reserve_crashkernel() powerpc/kernel/prom.c::early_init_devtree() powerpc/mm/init_32.c::MMU_init() powerpc/mm/tlb_nohash.c::__early_init_mmu() powerpc/platforms/ps3/mm.c::ps3_mm_add_memory() powerpc/platforms/embedded6xx/wii.c::wii_memory_fixups() sh/kernel/machine_kexec.c::reserve_crashkernel() * x86/kernel/e820.c::memblock_x86_fill() was directly setting memblock_can_resize before populating memblock and calling analyze afterwards. Call memblock_allow_resize() before start populating. memblock_can_resize is now static inside memblock.c. Signed-off-by: NTejun Heo <tj@kernel.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Michal Simek <monstr@monstr.eu> Cc: Paul Mundt <lethal@linux-sh.org> Cc: "David S. Miller" <davem@davemloft.net> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: "H. Peter Anvin" <hpa@zytor.com>
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由 Tejun Heo 提交于
memblock_init() initializes arrays for regions and memblock itself; however, all these can be done with struct initializers and memblock_init() can be removed. This patch kills memblock_init() and initializes memblock with struct initializer. The only difference is that the first dummy entries don't have .nid set to MAX_NUMNODES initially. This doesn't cause any behavior difference. Signed-off-by: NTejun Heo <tj@kernel.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Michal Simek <monstr@monstr.eu> Cc: Paul Mundt <lethal@linux-sh.org> Cc: "David S. Miller" <davem@davemloft.net> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: "H. Peter Anvin" <hpa@zytor.com>
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由 Tejun Heo 提交于
24aa0788 (memblock, x86: Replace memblock_x86_reserve/free_range() with generic ones) removed arch/x86/include/asm/memblock.h and dropped its inclusion from include/linux/memblock.h which breaks other architectures which depended on the generic memblock.h pulling in the arch specific one. However, the proper fix isn't adding back the asm inclusion. memblock doesn't have any arch dependent part and doesn't need arch specific header file and asm/memblock.h files are either practically empty or contain mostly unrelated arch specific stuff. * In microblaze, sh, powerpc, sparc and openrisc, asm/memblock.h is either empty or just contains unused MEMBLOCK_DBG() macro. Remove them. * In arm and unicore32, asm/memblock.h contains arch specific stuff. Include it directly from its users. It might be a good idea to rename the header file to avoid confusion. Signed-off-by: NTejun Heo <tj@kernel.org> Reported-by: N"H. Peter Anvin" <hpa@zytor.com> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Michal Simek <monstr@monstr.eu> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mundt <lethal@linux-sh.org> Cc: "David S. Miller" <davem@davemloft.net> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn>
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- 08 12月, 2011 10 次提交
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由 Catalin Marinas 提交于
This patch adds the ARM_LPAE and ARCH_PHYS_ADDR_T_64BIT Kconfig entries allowing LPAE support to be compiled into the kernel. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Will Deacon 提交于
Memory banks living outside of the 32-bit physical address space do not have a 1:1 pa <-> va mapping and therefore the __va macro may wrap. This patch ensures that such banks are marked as highmem so that the Kernel doesn't try to split them up when it sees that the wrapped virtual address overlaps the vmalloc space. Signed-off-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Acked-by: NNicolas Pitre <nico@linaro.org>
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由 Catalin Marinas 提交于
With LPAE, the pgd is a separate page table with entries pointing to the pmd. The identity_mapping_add() function needs to ensure that the pgd is populated before populating the pmd level. The do..while blocks now loop over the pmd in order to have the same implementation for the two page table formats. The pmd_addr_end() definition has been removed and the generic one used instead. The pmd clean-up is done in the pgd_free() function. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Catalin Marinas 提交于
With LPAE, TTBRx registers are 64-bit. The ASID is stored in TTBR0 rather than a separate Context ID register. This patch makes the necessary changes to handle context switching on LPAE. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Catalin Marinas 提交于
The DFSR and IFSR register format is different when LPAE is enabled. In addition, DFSR and IFSR have similar definitions for the fault type. This modifies the fault code to correctly handle the new format. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Catalin Marinas 提交于
This patch adds the MMU initialisation for the LPAE page table format. The swapper_pg_dir size with LPAE is 5 rather than 4 pages. A new proc-v7-3level.S file contains the TTB initialisation, context switch and PTE setting code with the LPAE. The TTBRx split is based on the PAGE_OFFSET with TTBR1 used for the kernel mappings. The 36-bit mappings (supersections) and a few other memory types in mmu.c are conditionally compiled. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Catalin Marinas 提交于
This patch modifies the pgd/pmd/pte manipulation functions to support the 3-level page table format. Since there is no need for an 'ext' argument to cpu_set_pte_ext(), this patch conditionally defines a different prototype for this function when CONFIG_ARM_LPAE. The patch also introduces the L_PGD_SWAPPER flag to mark pgd entries pointing to pmd tables pre-allocated in the swapper_pg_dir and avoid trying to free them at run-time. This flag is 0 with the classic page table format. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Catalin Marinas 提交于
This patch modifies the proc-v7.S file so that it only contains code shared between classic MMU and LPAE. The non-common code is factored out into a separate file. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Catalin Marinas 提交于
The FSR structure is different with LPAE and this patch moves the classic MMU specific definition to a separate fsr-2level.c file that is included in fault.c. It also moves the fsr_fs and FSR bits to the fault.h file. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Catalin Marinas 提交于
With the arch/arm code conversion to pgtable-nopud.h, the section and supersection (un|re)map code triggers compiler warnings on UP systems. This is caused by pmd_offset() being given a pgd_t argument rather than a pud_t one. This patch makes the necessary conversion with the assumption that the pud is folded into the pgd. The page table setting code only loops over the pmd which is enough with the classic page tables. This code is not compiled when LPAE is enabled. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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- 06 12月, 2011 6 次提交
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由 Will Deacon 提交于
The ARM SMP booting code allocates a temporary set of page tables containing an identity mapping of the kernel image and provides this to secondary CPUs for initial booting. In reality, we only need to include the __turn_mmu_on function in the identity mapping since the rest of the kernel is executing from virtual addresses after this point. This patch adds __turn_mmu_on to the .idmap.text section, allowing the SMP booting code to use the idmap_pgd directly and not have to populate its own set of page table. As a result of this patch, we can make the identity_mapping_add function static (since it is only used within mm/idmap.c) and also remove the identity_mapping_del function. The identity map population is moved to an early initcall so that it is setup in time for secondary CPU bringup. Reviewed-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NWill Deacon <will.deacon@arm.com>
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由 Will Deacon 提交于
For soft-rebooting a system, it is necessary to map the MMU-off code with an identity mapping so that execution can continue safely once the MMU has been switched off. Currently, switch_mm_for_reboot takes out a 1:1 mapping from 0x0 to TASK_SIZE during reboot in the hope that the reset code lives at a physical address corresponding to a userspace virtual address. This patch modifies the code so that we switch to the idmap_pgd tables, which contain a 1:1 mapping of the cpu_reset code. This has the advantage of only remapping the code that we need and also means we don't need to worry about allocating a pgd from an atomic context in the case that the physical address of the cpu_reset code aliases with the virtual space used by the kernel. Acked-by: NDave Martin <dave.martin@linaro.org> Reviewed-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NWill Deacon <will.deacon@arm.com>
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由 Will Deacon 提交于
The CPU reset functions disable the MMU and therefore must be executed with an identity mapping in place. This patch places the CPU reset functions into the .idmap.text section, causing the idmap code to include them as part of the identity mapping. Acked-by: NDave Martin <dave.martin@linaro.org> Signed-off-by: NWill Deacon <will.deacon@arm.com>
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由 Will Deacon 提交于
When disabling and re-enabling the MMU, it is necessary to take out an identity mapping for the code that manipulates the SCTLR in order to avoid it disappearing from under our feet. This is useful when soft rebooting and returning from CPU suspend. This patch allocates a set of page tables during boot and populates them with an identity mapping for the .idmap.text section. This means that users of the identity map do not need to manage their own pgd and can instead annotate their functions with __idmap or, in the case of assembly code, place them in the correct section. Acked-by: NDave Martin <dave.martin@linaro.org> Reviewed-by: NCatalin Marinas <catalin.marinas@arm.com> Tested-by: NLorenzo Pieralisi <Lorenzo.Pieralisi@arm.com> Signed-off-by: NWill Deacon <will.deacon@arm.com>
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由 Kautuk Consul 提交于
Commit d065bd81 (mm: retry page fault when blocking on disk transfer) and commit 37b23e05 (x86,mm: make pagefault killable) The above commits introduced changes into the x86 pagefault handler for making the page fault handler retryable as well as killable. These changes reduce the mmap_sem hold time, which is crucial during OOM killer invocation. Port these changes to ARM. Without these changes, my ARM board encounters many hang and livelock scenarios. After applying this patch, OOM feature performance improves according to my testing. Signed-off-by: NKautuk Consul <consul.kautuk@gmail.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Rob Herring 提交于
Similar to other architectures, this adds topdown mmap support in user process address space allocation policy. This allows mmap sizes greater than 2GB. This support is largely copied from MIPS and the generic implementations. The address space randomization is moved into arch_pick_mmap_layout. Tested on V-Express with ubuntu and a mmap test from here: https://bugs.launchpad.net/bugs/861296Signed-off-by: NRob Herring <rob.herring@calxeda.com> Acked-by: NNicolas Pitre <nico@linaro.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 29 11月, 2011 1 次提交
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由 Michael S. Tsirkin 提交于
arm copied pci_iomap from generic code, probably to avoid pulling the rest of iomap.c in. Since that's in a separate file now, we can reuse the common implementation. Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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- 27 11月, 2011 5 次提交
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由 Nicolas Pitre 提交于
Now that we have all the static mappings from iotable_init() located in the vmalloc area, it is trivial to optimize ioremap by reusing those static mappings when the requested physical area fits in one of them, and so in a generic way for all platforms. Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org> Tested-by: NStephen Warren <swarren@nvidia.com> Tested-by: NKevin Hilman <khilman@ti.com> Tested-by: NJamie Iles <jamie@jamieiles.com>
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由 Nicolas Pitre 提交于
Firstly, there is no need to have a double pointer here as we're only walking the vmlist and not modifying it. Secondly, for the same reason, we don't need a write lock but only a read lock here, since the lock only protects the coherency of the list nothing else. Lastly, the reason for holding a lock is not what the comment says, so let's remove that misleading piece of information. Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
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由 Nicolas Pitre 提交于
In order to remove the build time variation between different SOCs with regards to VMALLOC_END, the iotable mappings are now allocated inside the vmalloc region. This allows for VMALLOC_END to be identical across all machines. The value for VMALLOC_END is now set to 0xff000000 which is right where the consistent DMA area starts. To accommodate all static mappings on machines with possible highmem usage, the default vmalloc area size is changed to 240 MB so that VMALLOC_START is no higher than 0xf0000000 by default. Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org> Tested-by: NStephen Warren <swarren@nvidia.com> Tested-by: NKevin Hilman <khilman@ti.com> Tested-by: NJamie Iles <jamie@jamieiles.com>
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由 Sumit Bhattacharya 提交于
dma_alloc_coherent wants to split pages after allocation in order to reduce the memory footprint. This does not work well with GFP_COMP pages, so drop this flag before allocation. This patch is ported from arch/avr32 (commit 3611553e). [swarren: s/HUGETLB_PAGE/HUGETLBFS/ in comment, minor comment cleanup] Signed-off-by: NSumit Bhattacharya <sumitb@nvidia.com> Tested-by: NVarun Colbert <vcolbert@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Rob Herring 提交于
There are already cache type decoding functions, so use those instead of custom decode code which only works for ARMv6. Signed-off-by: NRob Herring <rob.herring@calxeda.com> Acked-by: NNicolas Pitre <nico@linaro.org> Acked-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 21 11月, 2011 2 次提交
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由 Catalin Marinas 提交于
Commit 99d1717d (ARM: Add init_consistent_dma_size()) introduces dynamic allocation of the consistent_pte array. The number of PTEs should be calculated based on the number of PMD entries rather than PGD, hence the PMD_SHIFT. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Cc: Jon Medhurst <tixy@yxit.co.uk> Acked-by: NNicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Will Deacon 提交于
The Kconfig options for the PL310 errata workarounds do not use a consistent naming scheme for either the config option or the bool description. This patch tidies up the options by ensuring that the bool descriptions are prefixed with "PL310 errata:" and the config options are prefixed with PL310_ERRATA_, making it much clearer in menuconfig as to what the workarounds are for. Signed-off-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 19 11月, 2011 2 次提交
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由 Nicolas Pitre 提交于
Some upcoming changes must know the VMALLOC_START value, which is based on high_memory, before bootmem_init() is called. The best location to set it is in sanity_check_meminfo() where the needed computation is already done, and in the non MMU case it is trivial to do now that the meminfo array is already sorted at that point. Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
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由 Nicolas Pitre 提交于
The meminfo array has to be sorted before sanity_check_meminfo() in arch/arm/mm/mmu.c is called for it to work properly. This also allows for a simpler find_limits() in arch/arm/mm/init.c. The sort is moved to arch/arm/kernel/setup.c because that's where the meminfo array is populated. Eventually this should be improved upon to make the memory bank parser a bit more robust against problems such as overlapping memory ranges. Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
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- 11 11月, 2011 1 次提交
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由 Russell King 提交于
setup_mm_for_reboot() doesn't make use of its argument, so remove it. Acked-by: NNicolas Pitre <nico@linaro.org> Acked-by: NWill Deacon <will.deacon@arm.com> Acked-by: NH Hartley Sweeten <hsweeten@visionengravers.com> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 01 11月, 2011 2 次提交
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由 Paul Gortmaker 提交于
These files all make use of one of the EXPORT_SYMBOL variants or the THIS_MODULE macro. So they will need <linux/export.h> Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
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由 Paul Gortmaker 提交于
Building these files does not reveal a hidden need for any of these. Since module.h brings in the whole kitchen sink, it just needlessly adds 30k+ lines to the cpp burden. There are probably lots more, but ARM files of mach-* and plat-* don't get coverage via a simple yesconfig build. They will have to be cleaned up and tested via using their respective configs. Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
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- 31 10月, 2011 3 次提交
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由 Sascha Hauer 提交于
The patch merges the build of imx3 and imx6. The Kconfig symbol ARCH_IMX_V6_V7 is introduced to replace ARCH_MX3 and ARCH_MX6. Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Shawn Guo 提交于
It adds generic device tree based machine support for imx6q. Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Rob Herring 提交于
This adds basic support for the Calxeda Highbank platform. Signed-off-by: NRob Herring <rob.herring@calxeda.com> Reviewed-by: NJamie Iles <jamie@jamieiles.com> Reviewed-by: NShawn Guo <shawn.guo@linaro.org>
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