[Description]
By default we can now set
ODM_MEM_VBLANK_PWR_MODE=1
Signed-off-by: NAlvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

LVDS support was implemented in DC a while ago.  Just DAC
support is left to do.
Reviewed-by: NEvan Quan <evan.quan@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
HUBP_UNBOUNDED_REQ_MODE and CURSOR_REQ_MODE are normally set together.
In hubp32_prepare_subvp_buffering() call, CURSOR_REQ_MODE is set based on
whether SubVP is enabled or not.  For non MPO case, both REQ_MODE
registers are set to 1.  But since SubVP is not enabled, then
CURSOR_REQ_MODE is set to 0, overriding the previous value.

[How]
Do not set CURSOR_REQ_MODE to 0 if SubVP is not enabled.  This
will allow CURSOR_REQ_MODE to stay as 1 in the non MPO case.
Add note to follow up and check case for single pipe MPO and
SubVP enabled as this would cause both REQ_MODE registers to be
set to 0 but SubVP enabled would override CURSOR_REQ_MODE to 1.
Signed-off-by: NSamson Tam <Samson.Tam@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

We know that "grbm_soft_reset" is true because we're already inside an
if (grbm_soft_reset) condition.  No need to test again.
Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Use the per asic offsets so the we don't have to have
asic specific logic in the common code.
Reviewed-by: NLuben Tuikov <luben.tuikov@amd.com>
Reviewed-by: NYang Wang <kevinyang.wang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Set appropriate caps for DCN3.2.x.
Signed-off-by: NDillon Varone <dillon.varone@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

So we can eventaully use them in the common smu code for
accessing the SMU mailboxes without needing a lot of
per asic logic in the common code.
Reviewed-by: NYang Wang <kevinyang.wang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[How & Why]
To be enabled once PMFW supports it.
Signed-off-by: NDillon Varone <dillon.varone@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Enable the AGP aperture on chips with GMC v11.
Reviewed-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Check IP version rather than asic type.
Reviewed-by: NGuchun Chen <guchun.chen@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[WHY?]
If higher states have memory speed set to 0 MT/s currently they do not get set
to the highest value which can cause validation failures.

[HOW?]
Set unpopulated higher states to max value.
Signed-off-by: NDillon Varone <dillon.varone@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Drop all of the extra cases in the default case.
Reviewed-by: NGuchun Chen <guchun.chen@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Rather than asic type.
Reviewed-by: NGuchun Chen <guchun.chen@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

VBIOS default clock value was halved, so the hardcoded dtb value should be
halved as well.

dtb clock should come from SMU eventually, but now dtb clock switching is not
fully supported yet in SMU.

Halve the dtb hardcoded value for now to have UHBR10 light up. Will rely on
SMU for dtb clock switching once available. The w/a is for DCN32 only, DCN321
should adopt the original value.
Signed-off-by: NFangzhi Zuo <Jerry.Zuo@amd.com>
Acked-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NDillon Varone <dillon.varone@amd.com>
Signed-off-by: NFangzhi Zuo <Jerry.Zuo@amd.com>
Acked-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This patch will fix sdma doorbell issue on SDMA v6.0 and NBIO v7.7.0.
NBIO v7.7.0 uses a new reg function -- Common SDMA to allow a common
doorbell range for all SDMA queues, this is different to the old
NBIO version. This patch will add configuration for CSDMA and enable
SDMA doorbell function.
Signed-off-by: NXiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: NTim Huang <Tim.Huang@amd.com>
Reviewed-by: NHuang Rui <ray.huang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This patch will add CSDMA reg offsets for NBIO v7.7.0
Signed-off-by: NXiaojian Du <Xiaojian.Du@amd.com>
Acked-by: NRoman Li <roman.li@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

APU required to issue the enable GFX IMU message after IMU reset.
Signed-off-by: NHuang Rui <ray.huang@amd.com>
Reviewed-by: NTim Huang <Tim.Huang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

GC v11_0_1 asic needs to issue the EnableGfxImu message after start IMU.
Signed-off-by: NHuang Rui <ray.huang@amd.com>
Reviewed-by: NTim Huang <Tim.Huang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Update MP v13_0_4 register macro for SMU message

v2: squash in missed case (Alex)
Signed-off-by: NHuang Rui <ray.huang@amd.com>
Reviewed-by: NTim Huang <Tim.Huang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This adds mmhub v3_0_1 ip block support

v2: rebase (Alex)
Signed-off-by: NHuang Rui <ray.huang@amd.com>
Reviewed-by: NTim Huang <Tim.Huang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Add mmhub v3_0_1 headers, because there are many differeces with v3_0_0.

v2: squash in updates (Alex)
Signed-off-by: NHuang Rui <ray.huang@amd.com>
Reviewed-by: NTim Huang <Tim.Huang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Switch to use the callback function to poll the reset status on IMU.
Because it will have different sequency on other ASICs.

v2: drop unused variable (Alex)
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NHuang Rui <ray.huang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why?]
On wake from S3/S4, driver checks if DMUB is initialized. On S4 VBIOS loads
DMUB, and driver does not reload as it appears to be initialized already.

[How?]
Add a check for the DAL_FW bit to ensure that loaded FW is from driver and
not VBIOS.
Signed-off-by: NDillon Varone <dillon.varone@amd.com>
Signed-off-by: NFangzhi Zuo <Jerry.Zuo@amd.com>
Reviewed-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
Use correct clock source initialization routine for DCN32/321
Signed-off-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[WHY&HOW]
Change criteria for setting DTO source value, and always set it regardless of
the signal type.
Signed-off-by: NDillon Varone <dillon.varone@amd.com>
Acked-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NStanley.Yang <Stanley.Yang@amd.com>
Acked-by: NLijo Lazar <lijo.lazar@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Disable idle optimizations until SMU can handle them to prevent DMUB
timeout and subsequent system freeze
Signed-off-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: NJerry Zuo <jerry.zuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: NJerry Zuo <jerry.zuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Add support for watermark table transfers.
Signed-off-by: NAlvin Lee <alvin.lee2@amd.com>
Acked-by: NJerry Zuo <jerry.zuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Fixes to enable higher rate timings for DCN3.2.x.
Signed-off-by: NDillon Varone <dillon.varone@amd.com>
Signed-off-by: NChaitanya Dhere <chaitanya.dhere@amd.com>
Signed-off-by: NNevenko Stupar <Nevenko.Stupar@amd.com>
Acked-by: NJerry Zuo <jerry.zuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[WHY?]
DCN321 does not support FCLK DPM, and thus it should not send messages to
PMFW regarding it.
Signed-off-by: NDillon Varone <dillon.varone@amd.com>
Acked-by: NJerry Zuo <jerry.zuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

IMU has two work mode such as debug mode and mission mode. Current GC
v11_0_0 is using the debug mode.
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NHuang Rui <ray.huang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Use DTBCLK for valid pixel clock generation
Signed-off-by: NEric Bernstein <eric.bernstein@amd.com>
Acked-by: NJerry Zuo <jerry.zuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Description]
Need to add inst 5 for clk_src_regs because
there are 5 PHY instances in DCN32 & DCN321.
Signed-off-by: NAlvin Lee <alvin.lee2@amd.com>
Acked-by: NJerry Zuo <jerry.zuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Description]

Add USBC connector ID to align with new VBIOS parsing.

Add seperate DCN321 link encoder due to different PHY version affecting
DP ALT related registers.
Signed-off-by: NDillon Varone <dillon.varone@amd.com>
Acked-by: NJerry Zuo <jerry.zuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

GFX11 IP introduces new tiling mode. Various combinations of DCC
settings are possible and the most preferred settings must be exposed
for optimal use of the hardware.

add_gfx11_modifiers() is based on recommendation from Marek for the
preferred tiling modifier that are most efficient for the hardware.

v2: microtiling fix noticed by Marek
v3: keep Z tiling check
Signed-off-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

align the cg and pg settings between gc_v11_0 and gc_v11_2
Signed-off-by: NKenneth Feng <kenneth.feng@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why&How]
Add DCN32 to IP discovery to enable automatic initialization of AMDGPU
Display Manager
Signed-off-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Add Display Manager specific changes for DCN3.2.x.  DM
handles the interaction between the core DC modesetting
code and the drm modesetting infrastructure.
Signed-off-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>