1. 13 5月, 2014 3 次提交
    • C
      drm/i915/chv: Pipe select change for DP and HDMI · 44f37d1f
      Chon Ming Lee 提交于
      With additional of pipe C, current 1 bit registers for pipe select
      for HDMI and DP are no longer able to gather for 3 pipes. As a result,
      new bits location in the same registers are added.
      
      For HDMI, VLV uses bit 30, CHV uses bit 24-25.
      
      For DP, VLV uses bit 30, CHV uses bit 16-17.
      Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: NChon Ming Lee <chon.ming.lee@intel.com>
      Reviewed-by: NImre Deak <imre.deak@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      44f37d1f
    • C
      drm/i915/chv: Add phy supports for Cherryview · e4a1d846
      Chon Ming Lee 提交于
      Added programming phy layer for CHV based on "Application note for 1273
      CHV Display phy".
      
      v2: Rebase the code and do some cleanup.
      v3: Rework based on Ville review.
          -Fix the macro where the ch info need to swap, and add parens to ?
      	 operator.
      	-Fix wrong bit define for DPIO_PCS_SWING_CALC_0 and
      	 DPIO_PCS_SWING_CALC_1 and rename for meaningful.
          -Add some comments for CHV specific DPIO registers.
          -Change the dp margin registery value to decimal to align with the
      	 doc.
      	-Fix the not clearing some value in vlv_dpio_read before write again.
          -Create new hdmi/dp encoder function for chv instead of share with
      	valleyview.
      v4: Rebase the code after rename the DPIO registers define and upstream
      	change.
          Based on Ville review.
          -For unique transition scale selection, after Ville point out, look
      	 like the doc might wrong for the bit 26.  Use bit 27 for ch0 and
      	 ch1.
      	-Break up some dpio write value into two/three steps for readability.
      	-Remove unrelated change.
          -Add some shift define for some registers instead just give the hex
      	value.
          -Fix a bug where write to wrong VLV_TX_DW3.
      v5: Based on Ville review.
      	- Move tx lane latency optimal setting from chv_dp_pre_pll_enable to
      	  chv_pre_enable_dp, and chv_hdmi_pre_pll_enable to
      	  chv_hdmi_pre_enable respectively.
       	- Fix typo in one margin_reg_value for DP_TRAIN_VOLTAGE_SWING_400.
      	- Clear DPIO_TX_UNIQ_TRANS_SCALE_EN for DP and HDMI.
      	- Mask the old deemph and swing bits for hdmi.
      v6: Remove stub for pre_pll_enable for dp and hdmi.
      Signed-off-by: NChon Ming Lee <chon.ming.lee@intel.com>
      Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      [vsyrjala: Don't touch panel power sequencing on DP]
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: NImre Deak <imre.deak@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      e4a1d846
    • C
      drm/i915/chv: find the best divisor for the target clock v4 · ef9348c8
      Chon Ming Lee 提交于
      Based on the chv clock limit, find the best divisor.
      
      The divisor data has been verified with this spreadsheet.
      P1273_DPLL_Programming Spreadsheet.
      
      v2: Rebase the code and change the chv_find_best_dpll based on new
      standard way to use intel_PLL_is_valid.  Besides, clean up some extra
      variables.
      
      v3: Ville suggest better fixed point for m2 calculation.
      
      v4: -Add comment for the limit is compute using fast clock. (Ville)
      	-Don't pass the request clock to chv_clock, as the same function will
      	 be use clock readout, which doens't have request clock. (Ville)
      	-Add and use DIV_ROUND_CLOSEST_ULL to consistent with other clock
      	calculation. (Ville)
      	-Fix the dp m2 after m2 has stored fixed point. (Ville)
      Signed-off-by: NChon Ming Lee <chon.ming.lee@intel.com>
      [vsyrjala: Avoid div-by-zero in chv_clock()]
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: NImre Deak <imre.deak@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      ef9348c8
  2. 05 5月, 2014 2 次提交
  3. 23 4月, 2014 1 次提交
    • P
      drm/i915: get power domain in case the BIOS enabled eDP VDD · 63635217
      Paulo Zanoni 提交于
      If I unplug the eDP monitor, the BIOS of my machine will enable the
      VDD bit, then when the driver loads it will think VDD is enabled. It
      will detect that the eDP is not enabled and return false from
      intel_edp_init_connector. This will trigger a call to
      edp_panel_vdd_off_sync(), which trigger a WARN saying that the
      refcount of the power domain is less than zero.
      
      The problem happens because the driver gets a refcount whenever it
      enables the VDD bit, and puts the refcount whenever it disables the
      VDD bit. But on this case, the BIOS enabled VDD, so all we do is to
      call put() without calling get() first, so the code added is there to
      make sure we always have the get() in case the BIOS enabled the bit.
      
      This regression was introduced in
      commit e9cb81a2
      Author: Paulo Zanoni <paulo.r.zanoni@intel.com>
      Date:   Thu Nov 21 13:47:23 2013 -0200
      
          drm/i915: get a runtime PM reference when the panel VDD is on
      
      v2: - Rebase
      
      Tested-by: Chris Wilson <chris@chris-wilson.co.uk> (v1)
      Reviewed-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      Cc: stable@vger.kernel.org (v3.13+)
      Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
      Signed-off-by: NJani Nikula <jani.nikula@intel.com>
      63635217
  4. 10 4月, 2014 2 次提交
    • P
      drm/i915: Add support for DRRS to switch RR · 439d7ac0
      Pradeep Bhat 提交于
      This patch computes and stored 2nd M/N/TU for switching to different
      refresh rate dynamically. PIPECONF_EDP_RR_MODE_SWITCH bit helps toggle
      between alternate refresh rates programmed in 2nd M/N/TU registers.
      
      v2: Daniel's review comments
      Computing M2/N2 in compute_config and storing it in crtc_config
      
      v3: Modified reference to edp_downclock and edp_downclock_avail based on the
      changes made to move them from dev_private to intel_panel.
      
      v4: Modified references to is_drrs_supported based on the changes made to
      rename it to drrs_support.
      
      v5: Jani's review comments
      Removed superfluous return statements. Changed support for Gen 7 and above.
      Corrected indentation. Re-structured the code which finds crtc and connector
      from encoder. Changed some logs to be less verbose.
      
      v6: Modifying i915_drrs to include only intel connector as intel_dp can be
      derived from intel connector when required.
      
      v7: As per internal review comments, acquiring mutex just before accessing
      drrs RR. As per Chris's review comments, added documentation about the use
      of locking in the function.
      
      v8: Incorporated Jani's review comments.
      Removed reference to edp_downclock.
      
      v9: Jani's review comments. Modified comment in set_drrs. Changed index to
      type edp_drrs_refresh_rate_type. Check if PSR is enabled before setting
      registers fo DRRS.
      Signed-off-by: NPradeep Bhat <pradeep.bhat@intel.com>
      Signed-off-by: NVandana Kannan <vandana.kannan@intel.com>
      Cc: Jani Nikula <jani.nikula@linux.intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      439d7ac0
    • P
      drm/i915: Parse EDID probed modes for DRRS support · 4f9db5b5
      Pradeep Bhat 提交于
      This patch and finds out the lowest refresh rate supported for the resolution
      same as the fixed_mode.
      It also checks the VBT fields to see if panel supports seamless DRRS or not.
      Based on above data it marks whether eDP panel supports seamless DRRS or not.
      This information is needed for supporting seamless DRRS switch for certain
      power saving usecases. This patch is tested by enabling the DRM logs and
      user should see whether Seamless DRRS is supported or not.
      
      v2: Daniel's review comments
      Modified downclock deduction based on intel_find_panel_downclock
      
      v3: Chris's review comments
      Moved edp_downclock_avail and edp_downclock to intel_panel
      
      v4: Jani's review comments.
      Changed name of the enum edp_panel_type to drrs_support type.
      Change is_drrs_supported to drrs_support of type enum drrs_support_type.
      
      v5: Incorporated Jani's review comments
      Modify intel_dp_drrs_initialize to return downclock mode. Support for Gen7
      and above.
      
      v6: Incorporated Chris's review comments.
      Changed initialize to init in intel_drrs_initialize
      
      v7: Incorporated Jani's review comments.
      Removed edp_downclock and edp_downclock_avail. Return NULL explicitly.
      Make drrs_state and unnamed struct. Move Gen based check inside drrs_init.
      
      v8: Made changes to track PSR enable/disable throughout system use (instead
      of just in the init sequence) for disabling/enabling DRRS. Jani's review
      comments.
      
      v9: PSR tracking will be done as part of idleness detection patch. Removed
      PSR state tracker in i915_drrs. Jani's review comments.
      
      v10: Added log for DRRS not supported in drrs_init
      
      v11: Modification in drrs_init. suggested by Jani
      Signed-off-by: NPradeep Bhat <pradeep.bhat@intel.com>
      Signed-off-by: NVandana Kannan <vandana.kannan@intel.com>
      Cc: Jani Nikula <jani.nikula@linux.intel.com>
      Reviewed-by: NJani Nikula <jani.nikula@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      4f9db5b5
  5. 08 4月, 2014 1 次提交
  6. 02 4月, 2014 4 次提交
    • M
      drm: Replace crtc fb with primary plane fb (v3) · f4510a27
      Matt Roper 提交于
      Now that CRTC's have a primary plane, there's no need to track the
      framebuffer in the CRTC.  Replace all references to the CRTC fb with the
      primary plane's fb.
      
      This patch was generated by the Coccinelle semantic patching tool using
      the following rules:
      
              @@ struct drm_crtc C; @@
              -   (C).fb
              +   C.primary->fb
      
              @@ struct drm_crtc *C; @@
              -   (C)->fb
              +   C->primary->fb
      
      v3: Generate patch via coccinelle.  Actual removal of crtc->fb has been
          moved to a subsequent patch.
      
      v2: Fixup several lingering crtc->fb instances that were missed in the
          first patch iteration.  [Rob Clark]
      Signed-off-by: NMatt Roper <matthew.d.roper@intel.com>
      Reviewed-by: NRob Clark <robdclark@gmail.com>
      f4510a27
    • V
      drm/i915: Split dp post_disable hooks · 49277c31
      Ville Syrjälä 提交于
      Split the post_disable hooks for DP to g4x and vlv variants. We'll
      need another variant soon, so this should make it look a bit cleaner.
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: NJani Nikula <jani.nikula@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      49277c31
    • I
      drm/i915: vlv: get power domain for eDP vdd · 4e6e1a54
      Imre Deak 提交于
      Besides D0 device state we need the proper power wells to be on on
      some platforms, so get the port power domain reference instead of an RPM
      reference.
      Signed-off-by: NImre Deak <imre.deak@intel.com>
      Reviewed-by: NAntti Koskipää <antti.koskipaa@linux.intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      4e6e1a54
    • P
      drm/i915: don't read pp_ctrl_reg if we're suspended · efbc20ab
      Paulo Zanoni 提交于
      ... at edp_have_panel_vdd. Just return false, saying we don't have the
      panel VDD since the device is suspended.
      
      We started getting WARNs about this problem since the patch that
      started checking if we're suspended while reading registers.
      
      Example backtrace provided by Paulo:
      
      [   63.572201] [drm:hsw_enable_pc8] Enabling package C8+
      [   63.581831] [drm:i915_runtime_suspend] Device suspended
      [   63.664798] ------------[ cut here ]------------
      [   63.664824] WARNING: CPU: 3 PID: 828 at
      drivers/gpu/drm/i915/intel_uncore.c:47
      assert_device_not_suspended.isra.7+0x32/0x40 [i915]()
      [   63.664826] Device suspended
      [   63.664828] Modules linked in: ccm fuse ip6table_filter ip6_tables
      ebtable_nat ebtables arc4 ath9k_htc ath9k_common ath9k_hw mac80211 ath
      cfg80211 iTCO_wdt iTCO_vendor_support x86_pkg_temp_thermal coretemp
      microcode i2c_i801 e1000e pcspkr serio_raw lpc_ich ptp pps_core mei_me
      mei mfd_core dm_crypt i915 crc32_pclmul crc32c_intel
      ghash_clmulni_intel i2c_algo_bit drm_kms_helper drm video
      [   63.664867] CPU: 3 PID: 828 Comm: kworker/3:3 Not tainted 3.14.0+ #153
      [   63.664869] Hardware name: Intel Corporation Shark Bay Client
      platform/WhiteTip Mountain 1, BIOS HSWLPTU1.86C.0133.R00.1309172123
      09/17/2013
      [   63.664887] Workqueue: events edp_panel_vdd_work [i915]
      [   63.664889]  0000000000000009 ffff88009d745c28 ffffffff8167ec6f
      ffff88009d745c70
      [   63.664895]  ffff88009d745c60 ffffffff8106c8ed ffff880036278000
      00000000000c7204
      [   63.664900]  ffff88014f2d3040 ffff880036278070 0000000000000001
      ffff88009d745cc0
      [   63.664905] Call Trace:
      [   63.664911]  [<ffffffff8167ec6f>] dump_stack+0x4d/0x66
      [   63.664916]  [<ffffffff8106c8ed>] warn_slowpath_common+0x7d/0xa0
      [   63.664920]  [<ffffffff8106c95c>] warn_slowpath_fmt+0x4c/0x50
      [   63.664926]  [<ffffffff810bd6be>] ? mark_held_locks+0xae/0x130
      [   63.664941]  [<ffffffffa00d80d2>]
      assert_device_not_suspended.isra.7+0x32/0x40 [i915]
      [   63.664956]  [<ffffffffa00d99d2>] gen6_read32+0x32/0x120 [i915]
      [   63.664969]  [<ffffffffa00d99a0>] ? gen6_read8+0x120/0x120 [i915]
      [   63.664985]  [<ffffffffa0106f8f>] edp_have_panel_vdd+0x3f/0x50 [i915]
      [   63.665000]  [<ffffffffa01074e8>] edp_panel_vdd_off_sync+0x58/0x1c0 [i915]
      [   63.665004]  [<ffffffff8108a06c>] ? process_one_work+0x18c/0x560
      [   63.665018]  [<ffffffffa0107684>] edp_panel_vdd_work+0x34/0x50 [i915]
      [   63.665022]  [<ffffffff8108a0d7>] process_one_work+0x1f7/0x560
      [   63.665026]  [<ffffffff8108a06c>] ? process_one_work+0x18c/0x560
      [   63.665031]  [<ffffffff8108ae2b>] worker_thread+0x11b/0x3a0
      [   63.665035]  [<ffffffff8108ad10>] ? manage_workers.isra.21+0x2a0/0x2a0
      [   63.665039]  [<ffffffff810916fc>] kthread+0xfc/0x120
      [   63.665043]  [<ffffffff81091600>] ? kthread_create_on_node+0x230/0x230
      [   63.665048]  [<ffffffff8169082c>] ret_from_fork+0x7c/0xb0
      [   63.665052]  [<ffffffff81091600>] ? kthread_create_on_node+0x230/0x230
      [   63.665054] ---[ end trace 1250bcc890af9999 ]---
      [   63.665060] [drm:edp_panel_vdd_off_sync] Turning eDP VDD off
      [   63.665061] ------------[ cut here ]------------
      
      Testcase: igt/pm_pc8
      Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      efbc20ab
  7. 29 3月, 2014 1 次提交
    • D
      drm/i915: add locking to fixed panel edid probing · 4da98541
      Daniel Vetter 提交于
      With the recent addition of locking checks in
      
      commit 62ff94a5
      Author:     Daniel Vetter <daniel.vetter@ffwll.ch>
      AuthorDate: Thu Jan 23 22:18:47 2014 +0100
      
          drm/crtc-helper: remove LOCKING from kerneldoc
      
      drm_add_edid_modes started to WARN about the mode_config.mutex not
      being held in the lvds and dp initialization code.
      
      Now since this is init code locking is fairly redudant if it wouldn't
      be for the drm core registering sysfs files a bit early. And the
      locking WARNINGs nicely enforce that indeed all access to the mode
      lists are properly protected. And a full audit shows that only i915
      and gma500 touch the modes lists at init time.
      
      Hence I've opted to wrap up this entire mode detection sequence for
      fixed panels with the mode_config mutex for both lvds and edp outputs.
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      4da98541
  8. 24 3月, 2014 1 次提交
    • D
      drm/i915: add locking to fixed panel edid probing · 060c8778
      Daniel Vetter 提交于
      With the recent addition of locking checks in
      
      commit 62ff94a5
      Author:     Daniel Vetter <daniel.vetter@ffwll.ch>
      AuthorDate: Thu Jan 23 22:18:47 2014 +0100
      
          drm/crtc-helper: remove LOCKING from kerneldoc
      
      drm_add_edid_modes started to WARN about the mode_config.mutex not
      being held in the lvds and dp initialization code.
      
      Now since this is init code locking is fairly redudant if it wouldn't
      be for the drm core registering sysfs files a bit early. And the
      locking WARNINGs nicely enforce that indeed all access to the mode
      lists are properly protected. And a full audit shows that only i915
      and gma500 touch the modes lists at init time.
      
      Hence I've opted to wrap up this entire mode detection sequence for
      fixed panels with the mode_config mutex for both lvds and edp outputs.
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      060c8778
  9. 19 3月, 2014 1 次提交
  10. 18 3月, 2014 7 次提交
  11. 11 3月, 2014 1 次提交
    • V
      drm/i915: Make encoder cloning more flexible · bc079e8b
      Ville Syrjälä 提交于
      Currently we allow encoders to indicate whether they can be part of a
      cloned set with just one flag. That's not flexible enough to describe
      the actual hardware capabilities. Instead make it a bitmask of encoder
      types with which the current encoder can be cloned.
      
      For now we set the bitmask to allow DVO+DVO and DVO+VGA, which should
      match what the old boolean flag allowed. We will add some more cloning
      options in the future.
      
      Note that this patch also removes the encoder.possible_clones setting
      from encoder setup code - we compute this dynamically.
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: NRodrigo Vivi <rodrigo.vivi@gmail.com>
      [danvet: Add Ville's explanation why removing the encoder
      possible_clones is save.]
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      bc079e8b
  12. 08 3月, 2014 2 次提交
  13. 06 3月, 2014 3 次提交
  14. 14 2月, 2014 2 次提交
  15. 13 2月, 2014 3 次提交
  16. 07 2月, 2014 1 次提交
    • D
      drm/i915: Disable dp aux irq on g4x · 4e6b788c
      Daniel Vetter 提交于
      Apparently it's broken in the exact same way as the gmbus irq. For
      reference of the full story see
      
      commit c12aba5a
      Author: Jiri Kosina <jkosina@suse.cz>
      Date:   Tue Mar 19 09:56:57 2013 +0100
      
          drm/i915: stop using GMBUS IRQs on Gen4 chips
      
      The effect is that we have a storm of unclaimed interrupts on the
      legacy irq line. If that one is used by a different device then the
      kernel will complain and rather quickly kill the irq source. Which
      breaks any device trying to actually use the legacy irq line.
      
      This regression has been introduced
      
      commit 4aeebd74
      Author: Daniel Vetter <daniel.vetter@ffwll.ch>
      Date:   Thu Oct 31 09:53:36 2013 +0100
      
          drm/i915: dp aux irq support for g4x/vlv
      
      Note that disabling MSI works around the issue, but we can't do that
      since apparently then the hw will miss interrupts. At least if
      relevant comments in i915_irq.c are accurate.
      
      v2: Cross-reference dp aux and gmbus gen4 comments.
      
      v3: Consolidate harder into i915_drv.h as suggested by Chris.
      
      Cc: Jani Nikula <jani.nikula@intel.com>
      Cc: Jiri Kosina <jkosina@suse.cz>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Reported-and-tested-by: NJiri Kosina <jkosina@suse.cz>
      Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      4e6b788c
  17. 31 1月, 2014 1 次提交
    • I
      drm/i915: vlv: fix DP PHY lockup due to invalid PP sequencer setup · 2cac613b
      Imre Deak 提交于
      Atm we setup the HW panel power sequencer logic both for eDP and DP
      ports. On eDP we then go on and start the power on sequence and commence
      with link training when it's ready. On DP we don't do the power on
      sequencing but do the link training immediately. At this point the DP
      PHY block gets stuck, since - supposedly - it is waiting for the power
      on sequence to finish. The actual register write that seems to hold off
      the PHY is PIPEX_PP_ON_DELAYS[Panel Control Port Select]. Writing here
      a non-0 value eventually sets PIPEX_PP_STATUS[Require Asset Status] to
      1 and blocks the PHY until the panel power on is ready.
      
      Fix this by not doing any PP sequencing setup for DP ports.
      
      Thanks to Ville Syrjälä, Jesse Barnes and Todd Previte for the help in
      tracking this down.
      
      Note that on older gmch platforms (where we have lvds instead of edp)
      we've hacked around this by writing the magic ABCD unlock key to PP
      registers, which disables the hw sanity checks.
      
      For edp all platforms thus far had the pch split, with the edp port in
      the north display complex and the PP registers on the pch the hw
      sanity checks (expressed through the "Require Asset Status" bit) was
      never functional, hence never a real issue.
      
      This regression has been introduce in
      
      commit bf13e81b
      Author: Jani Nikula <jani.nikula@intel.com>
      Date:   Fri Sep 6 07:40:05 2013 +0300
      
          drm/i915: add support for per-pipe power sequencing on vlv
      Signed-off-by: NImre Deak <imre.deak@intel.com>
      [danvet: Add note about the bigger story here.]
      Cc: stable@vger.kernel.org
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      2cac613b
  18. 30 1月, 2014 1 次提交
  19. 28 1月, 2014 1 次提交
    • J
      drm/i915: move module parameters into a struct, in a new file · d330a953
      Jani Nikula 提交于
      With 20+ module parameters, I think referring to them via a struct
      improves clarity over just having a bunch of globals. While at it, move
      the parameter initialization and definitions into a new file
      i915_params.c to reduce clutter in i915_drv.c.
      
      Apart from the ill-named i915_enable_rc6, i915_enable_fbc and
      i915_enable_ppgtt parameters, for which we lose the "i915_" prefix
      internally, the module parameters now look the same both on the kernel
      command line and in code. For example, "i915.modeset".
      
      The downsides of the change are losing static on a couple of variables
      and not having the initialization and module_param_named() right next to
      each other. On the other hand, all module parameters are now defined in
      one place at i915_params.c. Plus you can do this to find all module
      parameter references:
      
      $ git grep "i915\." -- drivers/gpu/drm/i915
      
      v2:
      - move the definitions into a new file
      - s/i915_params/i915/
      - make i915_try_reset i915.reset, for consistency
      Signed-off-by: NJani Nikula <jani.nikula@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      d330a953
  20. 27 1月, 2014 1 次提交
    • R
      drm/i915: debugfs: Add support for probing DP sink CRC. · d2e216d0
      Rodrigo Vivi 提交于
      This debugfs interface will allow intel-gpu-tools test case
      to verify if screen has been updated properly on cases like PSR.
      
      v2: Accepted all Daniel's suggestions:
          * grab modeset lock
          * loop over connector and check DPMS on
          * return errors
          * use _eDP1 suffix for easy future extension
          * don't cache crc_supported neither latest crc
          * return crc as a full array and read it at once with aux.
          * use 0 to turn TEST_SINK off.
          * split the drm_helpers definitions in another patch.
      
      v3: Accepted 2 Damien's suggestion: remove h from printf hexa
          and return ENODEV when eDP not present instead of EAGAIN.
      
      v4: Accepted 2 Jani' s suggestion: 1 path for unlock and remove
          _retry from aux read.
      
      v5: removing last missing useless _retry (by Damien)
      
      Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
      Cc: Damien Lespiau <damien.lespiau@intel.com>
      Cc: Jani Nikula <jani.nikula@intel.com>
      Signed-off-by: NRodrigo Vivi <rodrigo.vivi@gmail.com>
      Reviewed-by: NDamien Lespiau <damien.lespiau@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      d2e216d0
  21. 25 1月, 2014 1 次提交