Update the pinctrl-bcm2835 driver to support being built as as a module
by converting it to a module_platform_driver() with the appropriate
module license, authors and description.
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
Reviewed-by: NNicolas Saenz Julienne <nsaenz@kernel.org>
Link: https://lore.kernel.org/r/20211019221127.1953001-1-f.fainelli@gmail.comSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

Ignore the same function with multiple groups.
Fix a typo in error print.

Fixes: 1948d5c5 ("pinctrl: Add pinmux & GPIO controller driver for a new SoC")
Signed-off-by: NRahul Tanwar <rtanwar@maxlinear.com>
Link: https://lore.kernel.org/r/20211020093815.20870-1-rtanwar@maxlinear.comSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

This change adds pinmux table entries for Tegra194
Signed-off-by: NPrathamesh Shete <pshete@nvidia.com>
Link: https://lore.kernel.org/r/20211018121815.3017-2-pshete@nvidia.comSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

Update lpdr pin-property for supported pins.

lpdr property help disable most basic driver fingers
leaving only minimal base driver finger.
Signed-off-by: NSuresh Mangipudi <smangipudi@nvidia.com>
Signed-off-by: NPrathamesh Shete <pshete@nvidia.com>
Link: https://lore.kernel.org/r/20211018121815.3017-1-pshete@nvidia.comSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

This commit includes pinctrl driver for Mediatek MT7986

The difference of pinctrl between mt7986a and mt7986b
is that pin-41 to pin-65 do not exist on mt7986b
Signed-off-by: NSam Shih <sam.shih@mediatek.com>
Acked-by: NSean Wang <sean.wang@kernel.org>
Link: https://lore.kernel.org/r/20211022124036.5291-3-sam.shih@mediatek.comSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

This updates bindings for MT7986 pinctrl driver. The
difference of pinctrl between mt7986a and mt7986b is that pin-41 to
pin-65 do not exist on mt7986b
Signed-off-by: NSam Shih <sam.shih@mediatek.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20211022124036.5291-2-sam.shih@mediatek.comSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

On lan966x platform when the switch gets reseted then also the sgpio
gets reseted. The fix for this is to extend also the sgpio driver to
call the reset driver which will be reseted only once by the first
driver that is probed.
Signed-off-by: NHoratiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: NSteen Hegelund <steen.hegelund@microchip.com>
Reviewed-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20211018085754.1066056-3-horatiu.vultur@microchip.comSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

This describes the new binding which allows to call a reset driver from
the pinctrl-microchip-sgpio driver.
Signed-off-by: NHoratiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20211018085754.1066056-2-horatiu.vultur@microchip.comSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

Stop specifying individual interrupts properties. Use #interrupt-cells
instead as we are switching qcom,spmi-mpp and qcom,ssbi-mpp to
hierarchical IRQ setup.
Signed-off-by: NDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20211008012524.481877-18-dmitry.baryshkov@linaro.orgSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

spmi-mpp did not have any irqchip support so consumers of this in
device tree would need to call gpio[d]_to_irq() in order to get the
proper IRQ on the underlying PMIC. IRQ chips in device tree should be
usable from the start without the consumer having to make an additional
call to get the proper IRQ on the parent. This patch adds hierarchical
IRQ chip support to the spmi-mpp code to correct this issue.
Signed-off-by: NDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211008012524.481877-17-dmitry.baryshkov@linaro.orgSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

The probing of this driver calls platform_irq_count, which will
setup all of the IRQs that are configured in device tree. In
preparation for converting this driver to be a hierarchical IRQ
chip, hardcode the IRQ count based on the hardware type so that all
the IRQs are not configured immediately and are configured on an
as-needed basis later in the boot process.

This change will also allow for the removal of the interrupts property
later in this patch series once the hierarchical IRQ chip support is in.

This patch also removes the generic qcom,spmi-mpp OF match since we
don't know the number of pins. All of the existing upstream bindings
already include the more-specific binding.
Signed-off-by: NDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211008012524.481877-16-dmitry.baryshkov@linaro.orgSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

ssbi-mpp did not have any irqchip support so consumers of this in
device tree would need to call gpio[d]_to_irq() in order to get the
proper IRQ on the underlying PMIC. IRQ chips in device tree should be
usable from the start without the consumer having to make an additional
call to get the proper IRQ on the parent. This patch adds hierarchical
IRQ chip support to the ssbi-mpp code to correct this issue.
Signed-off-by: NDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211008012524.481877-15-dmitry.baryshkov@linaro.orgSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

The probing of this driver calls platform_irq_count, which will
setup all of the IRQs that are configured in device tree. In
preparation for converting this driver to be a hierarchical IRQ
chip, hardcode the IRQ count based on the hardware type so that all
the IRQs are not configured immediately and are configured on an
as-needed basis later in the boot process.

This change will also allow for the removal of the interrupts property
later in this patch series once the hierarchical IRQ chip support is in.

This patch also removes the generic qcom,ssbi-mpp OF match since we
don't know the number of pins. All of the existing upstream bindings
already include the more-specific binding.
Signed-off-by: NDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211008012524.481877-14-dmitry.baryshkov@linaro.orgSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

Convert Qualcomm PMIC MPP bindings from .txt to .yaml format.
Signed-off-by: NDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20211008012524.481877-2-dmitry.baryshkov@linaro.orgSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add pinctrl data for ExynosAuto v9 SoC.

- GPA0, GPA1: 10, External wake up interrupt
- GPQ0: 2, XbootLDO, Speedy PMIC I/F
- GPB0, GPB1, GPB2, GPB3: 29, I2S 7 CH
- GPF0, GPF1, GPF2, GPF3,GPF4, GPF5, GPF6, GPF8: 52, FSYS
- GPG0, GPG1, GPG2, GPG3: 25, GPIO x 24, SMPL_INT
- GPP0, GPP1, GPP2, GPP3, GPP4, GPP5: 48, USI 12 CH
Signed-off-by: NChanho Park <chanho61.park@samsung.com>
Link: https://lore.kernel.org/r/20211008091443.44625-2-chanho61.park@samsung.comSigned-off-by: NKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20211017171912.5044-1-krzysztof.kozlowski@canonical.comSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

Convert rockchip,pinctrl.txt to YAML
Signed-off-by: NJohan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20211007144019.7461-1-jbx6244@gmail.comSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

Merge tag 'renesas-pinctrl-for-v5.16-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: renesas: Updates for v5.16 (take two)

  - Add MediaLB pins on R-Car H3, M3-W/W+, and M3-N.
  - Miscellaneous fixes and improvements.

Add a "sh_pfc: " prefix to common checker output that is not yet
prefixed by a subdriver-specific prefix ("<SoC-part-number>_pfc: "), for
easier grepping.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/9cf1dc9f895dc5fa74125dabddfe46fecf438b4f.1633615652.git.geert+renesas@glider.be

If some bits in a pin Pull-Up control register (PUPR) control pin
pull-down instead of pin pull-up, there are two pinmux_bias_reg entries:
a first one with the puen field filled in, listing pins with pull-up
functionality, and a second one with the pud field filled in, listing
pins with pull-down functionality.  On encountering the second entry,
where puen is NULL, the for-loop terminates early, causing the remaining
bias registers not to be checked.  In addition, sh_pfc_check_bias_reg()
does not handle such entries.

Fix this by treating pinmux_bias_reg.puen and pinmux_bias_reg.pud the
same.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/29526d06fa223cffd785cdb264b756a202b11cea.1633615652.git.geert+renesas@glider.be

Move the check for overlapping drive register fields from
sh_pfc_check_drive_reg() to sh_pfc_check_reg(), so it can be used for
other register types, too.  This requires passing the covered register
bits to sh_pfc_check_reg().
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/9d75057200890bbf31e226ffcc4514ecc5bc2c34.1633615652.git.geert+renesas@glider.be

The GENMASK(h, l) macro creates a contiguous bitmask starting at bit
position @l and ending at position @h, inclusive.

This did not trigger any error checks, as the individual register fields
cover at most 3 of the 4 available bits.

Fixes: 08df16e0 ("pinctrl: sh-pfc: checker: Add drive strength register checks")
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/8f82d6147fbe3367d4c83962480e97f58d9c96a2.1633615652.git.geert+renesas@glider.be

If some bits in a pin Pull-Up control register (PUPR) control pin
pull-down instead of pin pull-up, there are two pinmux_bias_reg entries:
a first one with the puen field filled in, listing pins with pull-up
functionality, and a second one with the pud field filled in, listing
pins with pull-down functionality.  On encountering the second entry,
where puen is NULL, the for-loop terminates early, causing the remaining
bias registers not to be saved/restored during PSCI system suspend.
Fortunately this does not trigger on any supported system yet, as PSCI
is only used on R-Car Gen3 and RZ/G2 systems, which all have separate
pin Pull-Enable (PUEN) and pin Pull-Up/Down control (PUD) registers.

Avoid this ever becoming a problem by treating pinmux_bias_reg.puen and
pinmux_bias_reg.pud the same.  Note that a register controlling both
pull-up and pull-down pins would be saved and restored twice, which is
harmless.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/59d2fbddff685b6a7a82ff17d2b37633e30e8860.1633615652.git.geert+renesas@glider.be

This adds pins, groups, and functions for MediaLB devices on Renesas
R-Car H3 and M3-W/N SoCs.
Signed-off-by: NAndrey Gusakov <andrey.gusakov@cogentembedded.com>
Signed-off-by: NVladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: NLUU HOAI <hoai.luu.ub@renesas.com>
Signed-off-by: NNikita Yushchenko <nikita.yoush@cogentembedded.com>
Link: https://lore.kernel.org/r/20211007200250.20661-1-nikita.yoush@cogentembedded.com
[geert: Fix automotive handling]
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Signed-off-by: NDu Huanpeng <dhu@hodcarrier.org>
Link: https://lore.kernel.org/r/1633879405-11658-1-git-send-email-dhu@hodcarrier.orgSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

Since the 'st,package' property is optional, outputting the "No package
detected" warning-level log when the property is absent is unsuitable.
Remove that log.
Signed-off-by: NFabien Dessenne <fabien.dessenne@foss.st.com>
Link: https://lore.kernel.org/r/20211008122454.617556-1-fabien.dessenne@foss.st.comSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add pin configuration and pinmux support for UniPhier NX1 SoC.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/1633518606-8298-4-git-send-email-hayashi.kunihiko@socionext.comSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

Update pinctrl binding document for UniPhier NX1 SoC.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/1633518606-8298-3-git-send-email-hayashi.kunihiko@socionext.comSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add extra audio I/O pinmux setting for LD11, LD20 and PXs3 SoCs.
Signed-off-by: NKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/1633518606-8298-2-git-send-email-hayashi.kunihiko@socionext.comSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add support for the GPIO controller in the pm6350 PMIC.
Signed-off-by: NLuca Weiss <luca@z3ntu.xyz>
Link: https://lore.kernel.org/r/20211007212444.328034-6-luca@z3ntu.xyzSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add pmic-gpio compatible string for pm6350 pmic.
Signed-off-by: NLuca Weiss <luca@z3ntu.xyz>
Link: https://lore.kernel.org/r/20211007212444.328034-5-luca@z3ntu.xyzSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

Merge tag 'renesas-pinctrl-for-v5.16-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: renesas: Updates for v5.16

  - Fix duplicate port register on RZ/G2L,
  - A minor improvement.

I2C pins's resistance value can be controlled by rsel register.
This patch provides rsel (resistance selection) setting on MT8195
Signed-off-by: NZhiyong Tao <zhiyong.tao@mediatek.com>
Reviewed-by: NChen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20210924080632.28410-6-zhiyong.tao@mediatek.comSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch supports rsel(resistance selection) feature for I2C pins.
It provides more resistance selection solution in different ICs.
It provides rsel define and si unit solution by identifying
"mediatek,rsel_resistance_in_si_unit" property in pio dtsi node.
Signed-off-by: NZhiyong Tao <zhiyong.tao@mediatek.com>
Reviewed-by: NChen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20210924080632.28410-5-zhiyong.tao@mediatek.comSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

Fix Camel spelling coding style to avoid checkpatch
warning in a following patch.
Signed-off-by: NZhiyong Tao <zhiyong.tao@mediatek.com>
Reviewed-by: NChen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20210924080632.28410-4-zhiyong.tao@mediatek.comSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

For supporting SI units in "bias-pull-down" & "bias-pull-up",
change pull up/down description
and add "mediatek,rsel_resistance_in_si_unit" description.
Signed-off-by: NZhiyong Tao <zhiyong.tao@mediatek.com>
Link: https://lore.kernel.org/r/20210924080632.28410-3-zhiyong.tao@mediatek.comSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch adds rsel define for mt8195.
Signed-off-by: NZhiyong Tao <zhiyong.tao@mediatek.com>
Acked-by: NRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210924080632.28410-2-zhiyong.tao@mediatek.comSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

Currently, if the GPIO is configured as output in the bootloader
and user changes the mode to input in HLOS, it would end up
getting configured as input/output. Functionally, this is fine;
however, there may be some requirements where the output needs
to be disabled so that it can be used only for input.

Add support to enable/disable output mode through "output-enable"
or "output-disable" pinctrl properties.
Signed-off-by: NSubbaraman Narayanamurthy <quic_subbaram@quicinc.com>
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1631588246-4811-3-git-send-email-quic_subbaram@quicinc.com
[Drop copyright change which is already upstrean in -rcN]
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Remove the duplicate port register 22h and replace it with missing port
register 21h.
Signed-off-by: NBiju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210922074140.22178-1-biju.das.jz@bp.renesas.com
Fixes: c4c4637e ("pinctrl: renesas: Add RZ/G2L pin and gpio controller driver")
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Add support for the pinconf DT property output-enable, output-disable
so that output can be enabled/disabled.
Signed-off-by: NSubbaraman Narayanamurthy <quic_subbaram@quicinc.com>
Acked-by: NRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1631588246-4811-2-git-send-email-quic_subbaram@quicinc.comSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

It's a porting of pinctrl-scuba driver from CAF msm-4.19 kernel.  The
egpio and wake bits are removed.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210923033224.29719-3-shawn.guo@linaro.orgSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>