- 17 4月, 2014 1 次提交
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由 Alex Deucher 提交于
Don't try and runtime suspend the APU in PX systems. We only want to power down the dGPU. v2: fix harder v3: fix stupid typo v4: consolidate runpm enablement to a single flag bugs: https://bugs.freedesktop.org/show_bug.cgi?id=75127 https://bugzilla.kernel.org/show_bug.cgi?id=72701Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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- 03 4月, 2014 1 次提交
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由 Dave Airlie 提交于
For runtime pm we'd never suspend with the modesetting hw turned on, so don't try and resume the modesetting hw, as that path will take locks that the interface that is causing us to wake up might also take. Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 02 4月, 2014 1 次提交
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由 Matt Roper 提交于
Now that CRTC's have a primary plane, there's no need to track the framebuffer in the CRTC. Replace all references to the CRTC fb with the primary plane's fb. This patch was generated by the Coccinelle semantic patching tool using the following rules: @@ struct drm_crtc C; @@ - (C).fb + C.primary->fb @@ struct drm_crtc *C; @@ - (C)->fb + C->primary->fb v3: Generate patch via coccinelle. Actual removal of crtc->fb has been moved to a subsequent patch. v2: Fixup several lingering crtc->fb instances that were missed in the first patch iteration. [Rob Clark] Signed-off-by: NMatt Roper <matthew.d.roper@intel.com> Reviewed-by: NRob Clark <robdclark@gmail.com>
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- 07 3月, 2014 1 次提交
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由 Alex Deucher 提交于
Moving the pm resume up in the init order to fix dpm seems to have regressed somes cases with the old pm code. Move it back to late resume. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 03 3月, 2014 2 次提交
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由 Christian König 提交于
Not needed any more. Signed-off-by: NChristian König <christian.koenig@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Christian König 提交于
No need to make it more complicated than necessary, just allocate the page tables as normal BO and flush whenever the address change. v2: update comments and function name v3: squash bug fixes, page directory and tables patch v4: rebased on Mareks changes Signed-off-by: NChristian König <christian.koenig@amd.com>
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- 28 2月, 2014 1 次提交
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由 Christian König 提交于
We no longer need to take the ring lock while checking for a gpu lockup, so just cleanup the code. Signed-off-by: NChristian König <christian.koenig@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
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- 09 1月, 2014 1 次提交
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由 Alex Deucher 提交于
This is used to hard reset the asic. If a soft reset is not able to reset things, a hard reset can be used. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 08 1月, 2014 1 次提交
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由 Rashika Kheria 提交于
Mark functions radeon_doorbell_init() and radeon_doorbell_fini() as static in drm/radeon/radeon_device.c because they are not used outside this file. This eliminates the following warning in drm/radeon/radeon_device.c: drivers/gpu/drm/radeon/radeon_device.c:252:5: warning: no previous prototype for ‘radeon_doorbell_init’ [-Wmissing-prototypes] drivers/gpu/drm/radeon/radeon_device.c:281:6: warning: no previous prototype for ‘radeon_doorbell_fini’ [-Wmissing-prototypes] Signed-off-by: NRashika Kheria <rashika.kheria@gmail.com> Reviewed-by: NJosh Triplett <josh@joshtriplett.org> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 25 12月, 2013 1 次提交
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由 Alex Deucher 提交于
We need more control over the ordering of dpm init with respect to the rest of the asic. Specifically, the SMC has to be initialized before the rlc and cg/pg. The pm code currently initializes late in the driver, but we need it to happen much earlier so move pm handling into the asic specific callbacks. This makes dpm more reliable and makes clockgating work properly on CIK parts and should help on SI parts as well. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 16 11月, 2013 1 次提交
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由 Andrew Lewycky 提交于
A single doorbell page is plenty for cik kms compute. Use a single page and manage doorbell allocation by individual doorbells rather than pages. Identify doorbells by their index rather than byte offset. Signed-off-by: NAndrew Lewycky <Andrew.Lewycky@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 09 11月, 2013 1 次提交
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由 Alex Deucher 提交于
Hawaii is a new CI-based dGPU. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 02 11月, 2013 3 次提交
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由 Christian König 提交于
Stop fiddling with jiffies, always wait for RADEON_FENCE_JIFFIES_TIMEOUT. Consolidate the two wait sequence implementations into just one function. Activate all waiters and remember if the reset was already done instead of trying to reset from only one thread. v2: clear reset flag earlier to avoid timeout in IB test Signed-off-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Dave Airlie 提交于
This hooks radeon up to the runtime PM system to enable dynamic power management for secondary GPUs in switchable and powerxpress laptops. v2: agd5f: clean up, add module parameter Signed-off-by: NDave Airlie <airlied@redhat.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Dave Airlie 提交于
This is a pre-requisite for runtime pm on powerxpress systems. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 23 9月, 2013 1 次提交
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由 Alex Deucher 提交于
The tests are only usable if the acceleration engines have been successfully initialized. Based on an initial patch from: Alex Ivanov <gnidorah@p0n4ik.tk> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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- 11 9月, 2013 2 次提交
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由 Alex Deucher 提交于
This adds spinlocks to protect access to other indirect register apertures. These indirect spaces are used pretty infrequently and we haven't had an reported problems, but better safe than sorry. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alex Deucher 提交于
smc registers are access indirectly via the main mmio aperture, so there may be problems with concurrent access. This adds a spinlock to protect access to this register space. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 31 8月, 2013 1 次提交
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由 Alex Deucher 提交于
Newer asics have a lot of vram so it's less of an issue to waste a little more space for the gart page table. This gives us some additional gart space before having to migrate to non-gart system ram for games, etc. where we use up most of vram. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 29 8月, 2013 1 次提交
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由 Dave Airlie 提交于
For optimus and powerxpress muxless we really want the GPU driver deciding when to power up/down the GPU, not userspace. This adds the ability for a driver to dynamically power up/down the GPU and remove the switcheroo from controlling it, the switcheroo reports the dynamic state to userspace also. It also adds 2 power domains, one for machine where the power switch is controlled outside the GPU D3 state, so the powerdown ordering is done correctly, and the second for the hdmi audio device to make sure it can resume for PCI config space accesses. v1.1: fix build with switcheroo off v2: add power domain support for radeon and v1 nvidia dsms v2.1: fix typo in off case v3: add audio power domain for hdmi audio + misc audio fixes v4: use PCI_SLOT macro, drop power reference on hdmi audio resume failure also. Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 08 8月, 2013 2 次提交
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由 Alex Deucher 提交于
We need proper locking in the driver when accessing instanced registers on CIK. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alex Deucher 提交于
When we reset the GPU, we need to properly tear down power management before reseting the GPU and then set it back up again after reset. Add the missing radeon_pm_[suspend|resume] calls to the gpu reset function. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 27 6月, 2013 1 次提交
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由 Alex Deucher 提交于
The doorbell aperture is a PCI BAR whose pages can be mapped to compute resources for things like wptrs for userspace queues. This patch maps the BAR and sets up a simple allocator to allocate pages from the BAR. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 26 6月, 2013 2 次提交
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由 Alex Deucher 提交于
register BAR is now at PCI BAR 5. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alex Deucher 提交于
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 12 6月, 2013 1 次提交
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由 Jerome Glisse 提交于
UVD ring can't use scratch thus it does need writeback buffer to keep a valid address or radeon_ring_backup will trigger a kernel fault. It's ok to not unpin the write back buffer on suspend as it leave in gtt and thus does not need eviction. v2: Fix the uvd case. Reported and tracked by Wojtek <wojtask9@wp.pl> Signed-off-by: NJerome Glisse <jglisse@redhat.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 30 5月, 2013 1 次提交
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由 Alex Deucher 提交于
This narrows the scope of the apple re-POST hack added in: drm/radeon: re-POST the asic on Apple hardware when booted via EFI That patch prevents UVD from working on macs when booted in EFI mode. The original patch fixed macbook2,1 systems which were r5xx and hence have no UVD. Limit the hack to those systems to prevent UVD breakage on newer systems. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=63935 Cc: Matthew Garrett <mjg59@srcf.ucam.org> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Acked-by: NMatthew Garrett <matthew.garrett@nebula.com>
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- 29 5月, 2013 2 次提交
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由 Alex Deucher 提交于
Skip checking crtcs in hardware without them. Avoids checking non-existent hardware. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alex Deucher 提交于
Newer asics have variable numbers of crtcs. Use that rather than the asic family to determine which crtcs to check. This avoids checking non-existent crtcs or missing crtcs on certain asics. Reviewed-by: NMichel Dänzer <michel.daenzer@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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- 20 5月, 2013 1 次提交
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由 Alex Deucher 提交于
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NChristian König <christian.koenig@amd.com>
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- 02 5月, 2013 1 次提交
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由 Jerome Glisse 提交于
This is to allow debugging of userspace program not freeing buffer after, which is basicly a memory leak. This print the list of all gem object along with their size and placement (VRAM,GTT,CPU) and with the pid of the task that created them. agd5f: add warning fix Signed-off-by: NJerome Glisse <jglisse@redhat.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 24 4月, 2013 1 次提交
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由 Alex Deucher 提交于
Golden registers are arrays of register settings from the hw team that need to be initialized at asic startup. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 09 4月, 2013 1 次提交
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由 Alex Deucher 提交于
Add a per-asic MC (memory controller) mask which holds the mak address mask the asic is capable of. Use this when calculating the vram and gtt locations rather using asic specific functions or limiting everything to 32 bits. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 20 2月, 2013 1 次提交
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由 Tim Gardner 提交于
Smatch anlysis: drivers/gpu/drm/radeon/atom.c:1242 atom_index_iio() error: potential null dereference 'ctx->iio'. (kzalloc returns null) Also cleaned up some checks before calls to kfree(). kfree(NULL) is OK. Cc: David Airlie <airlied@linux.ie> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Michel Dänzer" <michel.daenzer@amd.com> Cc: Dave Airlie <airlied@redhat.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: Jerome Glisse <jglisse@redhat.com> Cc: dri-devel@lists.freedesktop.org Signed-off-by: NTim Gardner <tim.gardner@canonical.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 02 2月, 2013 1 次提交
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由 Alex Deucher 提交于
Oland is a new asic in the SI family. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 31 1月, 2013 1 次提交
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由 Matt Fleming 提交于
Originally 'efi_enabled' indicated whether a kernel was booted from EFI firmware. Over time its semantics have changed, and it now indicates whether or not we are booted on an EFI machine with bit-native firmware, e.g. 64-bit kernel with 64-bit firmware. The immediate motivation for this patch is the bug report at, https://bugs.launchpad.net/ubuntu-cdimage/+bug/1040557 which details how running a platform driver on an EFI machine that is designed to run under BIOS can cause the machine to become bricked. Also, the following report, https://bugzilla.kernel.org/show_bug.cgi?id=47121 details how running said driver can also cause Machine Check Exceptions. Drivers need a new means of detecting whether they're running on an EFI machine, as sadly the expression, if (!efi_enabled) hasn't been a sufficient condition for quite some time. Users actually want to query 'efi_enabled' for different reasons - what they really want access to is the list of available EFI facilities. For instance, the x86 reboot code needs to know whether it can invoke the ResetSystem() function provided by the EFI runtime services, while the ACPI OSL code wants to know whether the EFI config tables were mapped successfully. There are also checks in some of the platform driver code to simply see if they're running on an EFI machine (which would make it a bad idea to do BIOS-y things). This patch is a prereq for the samsung-laptop fix patch. Cc: David Airlie <airlied@linux.ie> Cc: Corentin Chary <corentincj@iksaif.net> Cc: Matthew Garrett <mjg59@srcf.ucam.org> Cc: Dave Jiang <dave.jiang@intel.com> Cc: Olof Johansson <olof@lixom.net> Cc: Peter Jones <pjones@redhat.com> Cc: Colin Ian King <colin.king@canonical.com> Cc: Steve Langasek <steve.langasek@canonical.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Konrad Rzeszutek Wilk <konrad@kernel.org> Cc: Rafael J. Wysocki <rjw@sisk.pl> Cc: <stable@vger.kernel.org> Signed-off-by: NMatt Fleming <matt.fleming@intel.com> Signed-off-by: NH. Peter Anvin <hpa@linux.intel.com>
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- 07 1月, 2013 1 次提交
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由 Maarten Lankhorst 提交于
vga-switcheroo with apple-gmux does not switch correctly on my system. The PCI configuration space is not restored correctly, resulting in MSI not working after switch. Only useful item in dmesg is: [ 33.922807] radeon 0000:01:00.0: Refused to change power state, currently in D3 I did some testing, dumping the difference in ms between first succesful switch from D3 to D0, and it seems that there is slightly more than 20 ms difference when the device is re-enabled through vga-switcheroo. So bump the re-enable d3 delay to 20 ms to handle this, which fixes msi not working on my system after switcheroo-ing. Default d3_delay value is PCI_PM_D3_WAIT, 10 ms. Signed-off-by: NMaarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 20 12月, 2012 3 次提交
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由 Jerome Glisse 提交于
Modeset path seems to conflict sometimes with the memory management leading to kernel deadlock. This move modesetting reset after GPU acceleration reset. Signed-off-by: NJerome Glisse <jglisse@redhat.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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由 Jerome Glisse 提交于
radeon_fence_wait_empty_locked should not trigger GPU reset as no place where it's call from would benefit from such thing and it actually lead to a kernel deadlock in case the reset is triggered from pm codepath. Instead force ring completion in place where it makes sense or return early in others. Signed-off-by: NJerome Glisse <jglisse@redhat.com> Reviewed-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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由 Jerome Glisse 提交于
Force all fence to signal if GPU reset failed so no process get stuck on waiting fence. Signed-off-by: NJerome Glisse <jglisse@redhat.com> Reviewed-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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