Add missing include files, missing static keyword, and use NULL instead
of 0, in order to fix warnings when compiling with C=1.
Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

Now that the only field in struct sys_timer is .init, delete the struct,
and replace the machine descriptor .timer field with the initialization
function itself.

This will enable moving timer drivers into drivers/clocksource without
having to place a public prototype of each struct sys_timer object into
include/linux; the intent is to create a single of_clocksource_init()
function that determines which timer driver to initialize by scanning
the device dtree, much like the proposed irqchip_init() at:
http://www.spinics.net/lists/arm-kernel/msg203686.html

Includes mach-omap2 fixes from Igor Grinberg.
Tested-by: NRobert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Also convert logical or to + for register offsets from base
addresses. This fixes a number of warnings currently seen in
linux-next:

warning: passing argument 2 of '__raw_writeb' makes pointer from
interger without cast.
Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Move to using a refined pr_fmt to avoid having to manually
prefix every message line with 'ts78xx'.

Changelog:
 v2: moved pr_fmt define ahead of includes as suggested by
	Hartley Sweeten to avoid use of leading undef
 v1: initial release
Signed-off-by: NAlexander Clouter <alex@digriz.org.uk>
Signed-off-by: NAndrew Lunn <andrew@lunn.ch>

Move ts78xx_fpga from /sys/power to /sys/firmware so that
we can remove the PM dependency.
Signed-off-by: NAlexander Clouter <alex@digriz.org.uk>
Signed-off-by: NAndrew Lunn <andrew@lunn.ch>

Changelog:
 v2: use DEFINE_RES_MEM as suggesed by Hartley Sweeten
 v1: inital release
Signed-off-by: NAlexander Clouter <alex@digriz.org.uk>
Signed-off-by: NAndrew Lunn <andrew@lunn.ch>

Signed-off-by: NAlexander Clouter <alex@digriz.org.uk>
Signed-off-by: NAndrew Lunn <andrew@lunn.ch>

Use the default partition parser, cmdlinepart, provided by the plat_nand driver.
Signed-off-by: NH Hartley Sweeten <hsweeten@visionengravers.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Acked-by: NAlexander Clouter <alex@digriz.org.uk>
Acked-by: NMarek Vasut <marek.vasut@gmail.com>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Hook these platforms restart code into the new restart hook rather than
using arch_reset().

In addition, convert calls to arm_machine_restart() to orion5x_restart()
to ensure that they continue to work as intended.
Acked-by: NNicolas Pitre <nico@linaro.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Recall the recently added prefix requirements:
 * "NAND_" for flags in nand.h, used in nand_chip.options
 * "NAND_BBT_" for flags in bbm.h, used in nand_chip.bbt_options
        or in nand_bbt_descr.options

Thus, I am changing NAND_USE_FLASH_BBT to NAND_BBT_USE_FLASH.

Again, this flag is found in bbm.h and so should NOT be used in the
"nand_chip.options" field.
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NArtem Bityutskiy <Artem.Bityutskiy@nokia.com>

This patch works with the following three flags from two headers (nand.h
and bbm.h):
  (1) NAND_USE_FLASH_BBT (nand.h)
  (2) NAND_USE_FLASH_BBT_NO_OOB (nand.h)
  (3) NAND_BBT_NO_OOB (bbm.h)

These flags are all related and interdependent, yet they were in
different headers. Flag (2) is simply the combination of (1) and (3) and
can be eliminated.

This patch accomplishes the following:
  * eliminate NAND_USE_FLASH_BBT_NO_OOB (i.e., flag (2))
  * move NAND_USE_FLASH_BBT (i.e., flag (1)) to bbm.h

It's important to note that because (1) and (3) are now both found in
bbm.h, they should NOT be used in the "nand_chip.options" field.

I removed a small section from the mtdnand DocBook because it referes to
NAND_USE_FLASH_BBT in nand.h, which has been moved to bbm.h.
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NArtem Bityutskiy <Artem.Bityutskiy@nokia.com>

Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>

Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NNicolas Pitre <nico@fluxnic.net>

Signed-off-by: NAlexander Clouter <alex@digriz.org.uk>
Signed-off-by: NNicolas Pitre <nico@fluxnic.net>

Signed-off-by: NAlexander Clouter <alex@digriz.org.uk>
[np: used min_t() as suggested by Sergei Shtylyov <sshtylyov@mvista.com>]
Signed-off-by: NNicolas Pitre <nico@fluxnic.net>

Originally the FPGA ID checking switch statement left disabled all the
TS implemented FPGA devices if the ID was unknown to it.  Michael Spang
created a fix in f9b1184e that changed the default to enable the devices
in the event TS silently release more revisions into the wild, this
unfortunately breaks custom FPGA bitstreams.

This patch amends the switch statement so that the TS devices are only
enabled if on the revision number is unknown (whilst the magic matches).

Changelog:
 v2: neater implementation and some cosmetic changes
 v1: initial release <20110305112937.GA22117@chipmunk>
Signed-off-by: NAlexander Clouter <alex@digriz.org.uk>
Signed-off-by: NNicolas Pitre <nico@fluxnic.net>

When the manufacturer increases the revision number the platform
devices for the RTC, NAND, and RNG disappear. We should assume
new revisions have these devices instead of assuming they do not.
Signed-off-by: NMichael Spang <mspang@csclub.uwaterloo.ca>
Signed-off-by: NNicolas Pitre <nico@fluxnic.net>

This patch makes the various mach dirs that use the plat-orion time
code pass in timer and bridge addresses explicitly, instead of having
plat-orion get those values by including a mach dir include file --
the latter mechanism is problematic if you want to support multiple
ARM platforms in the same kernel image.
Signed-off-by: NLennert Buytenhek <buytenh@secretlab.ca>
Signed-off-by: NNicolas Pitre <nico@fluxnic.net>

New FPGA revisions have been released and seen in the wild on the
platform, so it's time to update the list.
Signed-off-by: NAlexander Clouter <alex@digriz.org.uk>
Signed-off-by: NNicolas Pitre <nico@fluxnic.net>

The NAND supports 32bit reads and writes so lets stop shunting 8bit
chunks across the bus.

Doing a dumb 'dd' benchmark, this increases performance roughly like so:
 * read: 1.3MB/s to 3.4MB/s
 * write: 614kB/s to 882kB/s
Signed-off-by: NAlexander Clouter <alex@digriz.org.uk>
Signed-off-by: NNicolas Pitre <nico@fluxnic.net>

The type was IORESOURCE_IO which is not what is expected by
plat_nand_probe(). This device has not worked since 2d098a72
("mtd: plat_nand: request memory resource before doing ioremap").
Signed-off-by: NMichael Spang <mspang@csclub.uwaterloo.ca>
Signed-off-by: NNicolas Pitre <nico@fluxnic.net>

Since we're now using addruart to establish the debug mapping, we can
remove the io_pg_offst and phys_io members of struct machine_desc.

The various declarations were removed using the following script:

  grep -rl MACHINE_START arch/arm | xargs \
  sed -i '/MACHINE_START/,/MACHINE_END/ { /\.\(phys_io\|io_pg_offst\)/d }'

[ Initial patch was from Jeremy Kerr, example script from Russell King ]
Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
Acked-by: Eric Miao <eric.miao at canonical.com>

These three platforms didn't properly fill nr_chips in gen_nand 
registration and therefore depended on gen_nand bug fixed by commit 
81cbb0b1 ("mtd: gen_nand: fix support for 
multiple chips")
Signed-off-by: NMarek Vasut <marek.vasut@gmail.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Add hook so that the HW RNG source on the TS-78xx is available.
Signed-off-by: NAlexander Clouter <alex@digriz.org.uk>
Signed-off-by: NNicolas Pitre <nico@marvell.com>

Received official word finally from Technological Systems on which
FPGA ID's they have released unto the world.  Also an additional of
a dummy entry matching the FPGA ID of the Verilog template on our
wiki.
Signed-off-by: NAlexander Clouter <alex@digriz.org.uk>
Signed-off-by: NNicolas Pitre <nico@marvell.com>

Stefan Agner found his board comes with 0x00b480/0x02 but the main
board also has Rev B printed on it like my 0x00b480/0x03.  Some light
enum renaming was needed but it was to be expected.
Signed-off-by: NAlexander Clouter <alex@digriz.org.uk>
Signed-off-by: NNicolas Pitre <nico@marvell.com>

ts78xx add NAND support via plat_nand
Signed-off-by: NAlexander Clouter <alex@digriz.org.uk>
Signed-off-by: NNicolas Pitre <nico@cam.org>

amend RTC registering to not depend on ifdef's
Signed-off-by: NAlexander Clouter <alex@digriz.org.uk>
Signed-off-by: NNicolas Pitre <nico@cam.org>

Added checks to the platform_device_(register|add) calls so that if
a device failed to load it would then not later be unloaded; also
added the hooks so that it would not try to unload when the RTC
driver support is compiled out.
Signed-off-by: NAlexander Clouter <alex@digriz.org.uk>
Signed-off-by: NNicolas Pitre <nico@cam.org>

the FPGA on the TS-7800 provides access to a number of devices
and so we have to be careful when reprogramming it.  As we
are effectively turning a bus off/on we have to inform the
kernel that it should stop using anything provided by the
FPGA (currently only the RTC however the NAND, LCD, etc is
to come) before it's reprogrammed.

Once reprogramed, we can tell the kernel to (re)enable things
by checking the FPGA ID against a lookup table for what a
particular FPGA bitstream can provide.
Signed-off-by: NAlexander Clouter <alex@digriz.org.uk>

moved the MPP comments to the mpp area of the platform code
Signed-off-by: NAlexander Clouter <alex@digriz.org.uk>

The TS-7800's M25P40 is not available to the kernel, it's used
to load the initial bitstream onto the FPGA and so these hooks
point to nothing and need to be removed.
Signed-off-by: NAlexander Clouter <alex@digriz.org.uk>

Currently, there are two different fields in the
mv643xx_eth_platform_data struct that together describe the PHY
address -- one field (phy_addr) has the address of the PHY, but if
that address is zero, a second field (force_phy_addr) needs to be
set to distinguish the actual address zero from a zero due to not
having filled in the PHY address explicitly (which should mean
'use the default PHY address').

If we are a bit smarter about the encoding of the phy_addr field,
we can avoid the need for a second field -- this patch does that.
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

Signed-off-by: NSaeed Bishara <saeed@marvell.com>
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

This just leaves include/asm-arm/plat-* to deal with.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Signed-off-by: NAlexander Clouter <alex@digriz.org.uk>
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>