1. 24 6月, 2022 3 次提交
  2. 09 5月, 2022 1 次提交
  3. 05 5月, 2022 1 次提交
    • M
      regmap: Add bulk read/write callbacks into regmap_config · d77e7456
      Marek Vasut 提交于
      Currently the regmap_config structure only allows the user to implement
      single element register read/write using .reg_read/.reg_write callbacks.
      The regmap_bus already implements bulk counterparts of both, and is being
      misused as a workaround for the missing bulk read/write callbacks in
      regmap_config by a couple of drivers. To stop this misuse, add the bulk
      read/write callbacks to regmap_config and call them from the regmap core
      code.
      Signed-off-by: NMarek Vasut <marex@denx.de>
      Cc: Jagan Teki <jagan@amarulasolutions.com>
      Cc: Mark Brown <broonie@kernel.org>
      Cc: Maxime Ripard <maxime@cerno.tech>
      Cc: Robert Foss <robert.foss@linaro.org>
      Cc: Sam Ravnborg <sam@ravnborg.org>
      Cc: Thomas Zimmermann <tzimmermann@suse.de>
      To: dri-devel@lists.freedesktop.org
      Link: https://lore.kernel.org/r/20220430025145.640305-1-marex@denx.deSigned-off-by: NMark Brown <broonie@kernel.org>
      d77e7456
  4. 25 4月, 2022 1 次提交
  5. 04 4月, 2022 1 次提交
  6. 19 3月, 2022 2 次提交
  7. 17 2月, 2022 1 次提交
    • P
      regmap-irq: Update interrupt clear register for proper reset · d04ad245
      Prasad Kumpatla 提交于
      With the existing logic where clear_ack is true (HW doesn’t support
      auto clear for ICR), interrupt clear register reset is not handled
      properly. Due to this only the first interrupts get processed properly
      and further interrupts are blocked due to not resetting interrupt
      clear register.
      
      Example for issue case where Invert_ack is false and clear_ack is true:
      
          Say Default ISR=0x00 & ICR=0x00 and ISR is triggered with 2
          interrupts making ISR = 0x11.
      
          Step 1: Say ISR is set 0x11 (store status_buff = ISR). ISR needs to
                  be cleared with the help of ICR once the Interrupt is processed.
      
          Step 2: Write ICR = 0x11 (status_buff), this will clear the ISR to 0x00.
      
          Step 3: Issue - In the existing code, ICR is written with ICR =
                  ~(status_buff) i.e ICR = 0xEE -> This will block all the interrupts
                  from raising except for interrupts 0 and 4. So expectation here is to
                  reset ICR, which will unblock all the interrupts.
      
                  if (chip->clear_ack) {
                       if (chip->ack_invert && !ret)
                        ........
                       else if (!ret)
                           ret = regmap_write(map, reg,
                                  ~data->status_buf[i]);
      
      So writing 0 and 0xff (when ack_invert is true) should have no effect, other
      than clearing the ACKs just set.
      
      Fixes: 3a6f0fb7 ("regmap: irq: Add support to clear ack registers")
      Signed-off-by: NPrasad Kumpatla <quic_pkumpatl@quicinc.com>
      Reviewed-by: NCharles Keepax <ckeepax@opensource.cirrus.com>
      Tested-by: NMarek Szyprowski <m.szyprowski@samsung.com>
      Link: https://lore.kernel.org/r/20220217085007.30218-1-quic_pkumpatl@quicinc.comSigned-off-by: NMark Brown <broonie@kernel.org>
      d04ad245
  8. 14 2月, 2022 1 次提交
  9. 24 1月, 2022 1 次提交
  10. 08 1月, 2022 2 次提交
  11. 15 11月, 2021 1 次提交
  12. 24 10月, 2021 2 次提交
  13. 12 10月, 2021 1 次提交
    • Y
      regmap: Fix possible double-free in regcache_rbtree_exit() · 55e6d803
      Yang Yingliang 提交于
      In regcache_rbtree_insert_to_block(), when 'present' realloc failed,
      the 'blk' which is supposed to assign to 'rbnode->block' will be freed,
      so 'rbnode->block' points a freed memory, in the error handling path of
      regcache_rbtree_init(), 'rbnode->block' will be freed again in
      regcache_rbtree_exit(), KASAN will report double-free as follows:
      
      BUG: KASAN: double-free or invalid-free in kfree+0xce/0x390
      Call Trace:
       slab_free_freelist_hook+0x10d/0x240
       kfree+0xce/0x390
       regcache_rbtree_exit+0x15d/0x1a0
       regcache_rbtree_init+0x224/0x2c0
       regcache_init+0x88d/0x1310
       __regmap_init+0x3151/0x4a80
       __devm_regmap_init+0x7d/0x100
       madera_spi_probe+0x10f/0x333 [madera_spi]
       spi_probe+0x183/0x210
       really_probe+0x285/0xc30
      
      To fix this, moving up the assignment of rbnode->block to immediately after
      the reallocation has succeeded so that the data structure stays valid even
      if the second reallocation fails.
      Reported-by: NHulk Robot <hulkci@huawei.com>
      Fixes: 3f4ff561 ("regmap: rbtree: Make cache_present bitmap per node")
      Signed-off-by: NYang Yingliang <yangyingliang@huawei.com>
      Link: https://lore.kernel.org/r/20211012023735.1632786-1-yangyingliang@huawei.comSigned-off-by: NMark Brown <broonie@kernel.org>
      55e6d803
  14. 26 8月, 2021 1 次提交
  15. 02 8月, 2021 1 次提交
  16. 12 7月, 2021 2 次提交
  17. 14 6月, 2021 2 次提交
  18. 08 6月, 2021 2 次提交
  19. 07 6月, 2021 1 次提交
  20. 26 5月, 2021 1 次提交
  21. 21 5月, 2021 1 次提交
  22. 19 5月, 2021 1 次提交
  23. 14 5月, 2021 1 次提交
  24. 07 4月, 2021 1 次提交
  25. 31 3月, 2021 2 次提交
  26. 18 3月, 2021 1 次提交
    • G
      regmap-irq: Extend sub-irq to support non-fixed reg strides · 1066cfbd
      Guru Das Srinagesh 提交于
      Qualcomm's MFD chips have a top level interrupt status register and
      sub-irqs (peripherals).  When a bit in the main status register goes
      high, it means that the peripheral corresponding to that bit has an
      unserviced interrupt. If the bit is not set, this means that the
      corresponding peripheral does not.
      
      Commit a2d21848 ("regmap: regmap-irq: Add main status register
      support") introduced the sub-irq logic that is currently applied only
      when reading status registers, but not for any other functions like acking
      or masking. Extend the use of sub-irq to all other functions, with two
      caveats regarding the specification of offsets:
      
      - Each member of the sub_reg_offsets array should be of length 1
      - The specified offsets should be the unequal strides for each sub-irq
        device.
      
      In QCOM's case, all the *_base registers are to be configured to the
      base addresses of the first sub-irq group, with offsets of each
      subsequent group calculated as a difference from these addresses.
      
      Continuing from the example mentioned in the cover letter:
      
      	/*
      	 * Address of MISC_INT_MASK		= 0x1011
      	 * Address of TEMP_ALARM_INT_MASK	= 0x2011
      	 * Address of GPIO01_INT_MASK		= 0x3011
      	 *
      	 * Calculate offsets as:
      	 * offset_0 = 0x1011 - 0x1011 = 0       (to access MISC's
      	 * 					 registers)
      	 * offset_1 = 0x2011 - 0x1011 = 0x1000
      	 * offset_2 = 0x3011 - 0x1011 = 0x2000
      	 */
      
      	static unsigned int sub_unit0_offsets[] = {0};
      	static unsigned int sub_unit1_offsets[] = {0x1000};
      	static unsigned int sub_unit2_offsets[] = {0x2000};
      
      	static struct regmap_irq_sub_irq_map chip_sub_irq_offsets[] = {
      		REGMAP_IRQ_MAIN_REG_OFFSET(sub_unit0_offsets),
      		REGMAP_IRQ_MAIN_REG_OFFSET(sub_unit0_offsets),
      		REGMAP_IRQ_MAIN_REG_OFFSET(sub_unit0_offsets),
      	};
      
      	static struct regmap_irq_chip chip_irq_chip = {
      	--------8<--------
      	.not_fixed_stride = true,
      	.mask_base	  = MISC_INT_MASK,
      	.type_base	  = MISC_INT_TYPE,
      	.ack_base	  = MISC_INT_ACK,
      	.sub_reg_offsets  = chip_sub_irq_offsets,
      	--------8<--------
      	};
      Signed-off-by: NGuru Das Srinagesh <gurus@codeaurora.org>
      Link: https://lore.kernel.org/r/526562423eaa58b4075362083f561841f1d6956c.1615423027.git.gurus@codeaurora.orgSigned-off-by: NMark Brown <broonie@kernel.org>
      1066cfbd
  27. 10 3月, 2021 1 次提交
  28. 11 2月, 2021 3 次提交
  29. 21 1月, 2021 1 次提交