- 14 6月, 2019 7 次提交
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由 Shalom Toledo 提交于
Initialize the PTP physical hardware clock. Signed-off-by: NShalom Toledo <shalomt@mellanox.com> Acked-by: NJiri Pirko <jiri@mellanox.com> Reviewed-by: NPetr Machata <petrm@mellanox.com> Signed-off-by: NIdo Schimmel <idosch@mellanox.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Shalom Toledo 提交于
Implement physical hardware clock operations. Signed-off-by: NShalom Toledo <shalomt@mellanox.com> Acked-by: NJiri Pirko <jiri@mellanox.com> Reviewed-by: NPetr Machata <petrm@mellanox.com> Signed-off-by: NIdo Schimmel <idosch@mellanox.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Shalom Toledo 提交于
The MTPPS register provides the device PPS capabilities, configure the PPS in and out modules and holds the PPS in time stamp. Signed-off-by: NShalom Toledo <shalomt@mellanox.com> Acked-by: NJiri Pirko <jiri@mellanox.com> Reviewed-by: NPetr Machata <petrm@mellanox.com> Signed-off-by: NIdo Schimmel <idosch@mellanox.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Shalom Toledo 提交于
The MTUTC register configures the HW UTC counter. Signed-off-by: NShalom Toledo <shalomt@mellanox.com> Reviewed-by: NPetr Machata <petrm@mellanox.com> Acked-by: NJiri Pirko <jiri@mellanox.com> Signed-off-by: NIdo Schimmel <idosch@mellanox.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Shalom Toledo 提交于
Query free running clock PCI BAR and offsets during the pci_init. Signed-off-by: NShalom Toledo <shalomt@mellanox.com> Acked-by: NJiri Pirko <jiri@mellanox.com> Reviewed-by: NPetr Machata <petrm@mellanox.com> Signed-off-by: NIdo Schimmel <idosch@mellanox.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Shalom Toledo 提交于
Add two new bus operations for reading the hardware free running clock. Signed-off-by: NShalom Toledo <shalomt@mellanox.com> Acked-by: NJiri Pirko <jiri@mellanox.com> Reviewed-by: NPetr Machata <petrm@mellanox.com> Signed-off-by: NIdo Schimmel <idosch@mellanox.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Shalom Toledo 提交于
Add free running clock PCI BAR and offset to query firmware command. Signed-off-by: NShalom Toledo <shalomt@mellanox.com> Reviewed-by: NPetr Machata <petrm@mellanox.com> Acked-by: NJiri Pirko <jiri@mellanox.com> Signed-off-by: NIdo Schimmel <idosch@mellanox.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 05 6月, 2019 5 次提交
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由 David Ahern 提交于
Fail attempts to use nexthop objects with routes until support can be properly added. Signed-off-by: NDavid Ahern <dsahern@gmail.com> Reviewed-by: NIdo Schimmel <idosch@mellanox.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 David Ahern 提交于
Use helpers to access fib_nh and fib_nhs fields of a fib_info. Drop the fib_dev macro which is an alias for the first nexthop. Replacements: fi->fib_dev --> fib_info_nh(fi, 0)->fib_nh_dev fi->fib_nh --> fib_info_nh(fi, 0) fi->fib_nh[i] --> fib_info_nh(fi, i) fi->fib_nhs --> fib_info_num_path(fi) where fib_info_nh(fi, i) returns fi->fib_nh[nhsel] and fib_info_num_path returns fi->fib_nhs. Move the existing fib_info_nhc to nexthop.h and define the new ones there. A later patch adds a check if a fib_info uses a nexthop object, and defining the helpers in nexthop.h avoid circular header dependencies. After this all remaining open coded references to fi->fib_nhs and fi->fib_nh are in: - fib_create_info and helpers used to lookup an existing fib_info entry, and - the netdev event functions fib_sync_down_dev and fib_sync_up. The latter two will not be reused for nexthops, and the fib_create_info will be updated to handle a nexthop in a fib_info. Signed-off-by: NDavid Ahern <dsahern@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Jiri Pirko 提交于
Implement mlxfw status_notify op by passing notification down to devlink. Also notify about flash update begin and end. Signed-off-by: NJiri Pirko <jiri@mellanox.com> Reviewed-by: NIdo Schimmel <idosch@mellanox.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Jiri Pirko 提交于
Currently the error messages are printed to dmesg. Propagate them also to directly to user doing the flashing through extack. Signed-off-by: NJiri Pirko <jiri@mellanox.com> Reviewed-by: NIdo Schimmel <idosch@mellanox.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Jiri Pirko 提交于
Benefit from the devlink flash update implementation and ethtool fallback to it and move firmware flash implementation there. Signed-off-by: NJiri Pirko <jiri@mellanox.com> Reviewed-by: NIdo Schimmel <idosch@mellanox.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 31 5月, 2019 10 次提交
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由 Vadim Pasternak 提交于
Obtain SFP modules temperatures through MTMP register instead of MTBR register, because the first one utilizes shorter transaction buffer size for request. It improves performance in case low frequency interface (I2C) is used for communication with a chip. Signed-off-by: NVadim Pasternak <vadimp@mellanox.com> Acked-by: NJiri Pirko <jiri@mellanox.com> Signed-off-by: NIdo Schimmel <idosch@mellanox.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Vadim Pasternak 提交于
Extend sensor index size for Management Temperature Bulk Register (MTBR) and Management Temperature Register (MTMP) upto 12 bits in order to align registers description with new version of PRM document. Add define for base sensor index for SFP modules temperature reading for MTMP register. Signed-off-by: NVadim Pasternak <vadimp@mellanox.com> Acked-by: NJiri Pirko <jiri@mellanox.com> Signed-off-by: NIdo Schimmel <idosch@mellanox.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Vadim Pasternak 提交于
Add new attributes to hwmon object for exposing inter-connects temperature input, highest, reset_history temperatures and label. Temperatures are read from Management Temperature Register. The number of inter-connect devices is read from Management General Peripheral Information Register. Signed-off-by: NVadim Pasternak <vadimp@mellanox.com> Acked-by: NJiri Pirko <jiri@mellanox.com> Signed-off-by: NIdo Schimmel <idosch@mellanox.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Vadim Pasternak 提交于
Add MGPIR - Management General Peripheral Information Register, which allows software to query the hardware and firmware general information of peripheral entities as Gearboxes etc. Signed-off-by: NVadim Pasternak <vadimp@mellanox.com> Acked-by: NJiri Pirko <jiri@mellanox.com> Signed-off-by: NIdo Schimmel <idosch@mellanox.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Vadim Pasternak 提交于
Extend the size of sensor_index field of MTMP (Management Temperature Register), from 8 to 12 bits due to hardware change. Add define for sensor index for Gear Box (inter-connects) temperature reading. Signed-off-by: NVadim Pasternak <vadimp@mellanox.com> Acked-by: NJiri Pirko <jiri@mellanox.com> Signed-off-by: NIdo Schimmel <idosch@mellanox.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Ido Schimmel 提交于
The driver core first registers with the hwmon and thermal subsystems and only then proceeds to initialize the switch driver (e.g., mlxsw_spectrum). It is only during the last stage that the current firmware version is validated and a newer one flashed, if necessary. The above means that if a new firmware feature is utilized by the hwmon/thermal code, the driver will not be able to load. Solve this by re-ordering initializing the switch driver before registering with the hwmon and thermal subsystems. Signed-off-by: NIdo Schimmel <idosch@mellanox.com> Reported-by: NShalom Toledo <shalomt@mellanox.com> Acked-by: NJiri Pirko <jiri@mellanox.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Vadim Pasternak 提交于
Current implementation uses fixed size of I2C data transaction buffer. Allow to set size of I2C transactions according to I2C physical adapter capability. For that purpose adapter read and write size is obtained from the I2C physical adapter and buffer size is set according to the minimum of these two values. If adapter does not provide such info, default buffer size is to be used. It allows to improve performance of I2C access to silicon when long size transactions are used. Signed-off-by: NVadim Pasternak <vadimp@mellanox.com> Acked-by: NJiri Pirko <jiri@mellanox.com> Signed-off-by: NIdo Schimmel <idosch@mellanox.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Vadim Pasternak 提交于
Extend initialization flow with query request for firmware info in order to obtain firmware version info. This info is to be provided to minimal driver to support ethtool get_drvinfo() interface. Signed-off-by: NVadim Pasternak <vadimp@mellanox.com> Acked-by: NJiri Pirko <jiri@mellanox.com> Signed-off-by: NIdo Schimmel <idosch@mellanox.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Amit Cohen 提交于
Force of 56G is not supported by hardware in Ethernet devices. This configuration fails with a bad parameter error from firmware. Add check of this case. Instead of trying to set 56G with autoneg off, return a meaningful error. Fixes: 56ade8fe ("mlxsw: spectrum: Add initial support for Spectrum ASIC") Signed-off-by: NAmit Cohen <amitc@mellanox.com> Acked-by: NJiri Pirko <jiri@mellanox.com> Signed-off-by: NIdo Schimmel <idosch@mellanox.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Jiri Pirko 提交于
When identical rules are inserted, the latter one goes to C-TCAM. For that, a second eRP with the same mask is created. These 2 eRPs by the nature cannot be merged and also one cannot be parent of another. Teach mlxsw_sp_acl_erp_delta_fill() about this possibility and handle it gracefully. Reported-by: NAlex Kushnarov <alexanderk@mellanox.com> Fixes: c22291f7 ("mlxsw: spectrum: acl: Implement delta for ERP") Signed-off-by: NJiri Pirko <jiri@mellanox.com> Signed-off-by: NIdo Schimmel <idosch@mellanox.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 25 5月, 2019 1 次提交
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由 David Ahern 提交于
Move fib6_nh to the end of fib6_info and make it an array of size 0. Pass a flag to fib6_info_alloc indicating if the allocation needs to add space for a fib6_nh. The current code path always has a fib6_nh allocated with a fib6_info; with nexthop objects they will be separate. Signed-off-by: NDavid Ahern <dsahern@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 21 5月, 2019 1 次提交
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由 Thomas Gleixner 提交于
Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: NThomas Gleixner <tglx@linutronix.de> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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- 19 5月, 2019 2 次提交
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由 Vadim Pasternak 提交于
Prevent reading unsupported slave address from SFP EEPROM by testing Diagnostic Monitoring Type byte in EEPROM. Read only page zero of EEPROM, in case this byte is zero. If some SFP transceiver does not support Digital Optical Monitoring (DOM), reading SFP EEPROM slave address 0x51 could return an error. Availability of DOM support is verified by reading from zero page Diagnostic Monitoring Type byte describing how diagnostic monitoring is implemented by transceiver. If bit 6 of this byte is set, it indicates that digital diagnostic monitoring has been implemented. Otherwise it is not and transceiver could fail to reply to transaction for slave address 0x51 [1010001X (A2h)], which is used to access measurements page. Such issue has been observed when reading cable MCP2M00-xxxx, MCP7F00-xxxx, and few others. Fixes: 2ea10903 ("mlxsw: spectrum: Add support for access cable info via ethtool") Fixes: 4400081b ("mlxsw: spectrum: Fix EEPROM access in case of SFP/SFP+") Signed-off-by: NVadim Pasternak <vadimp@mellanox.com> Acked-by: NJiri Pirko <jiri@mellanox.com> Signed-off-by: NIdo Schimmel <idosch@mellanox.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Vadim Pasternak 提交于
Old Mellanox silicons, like switchx-2, switch-ib do not support reading QSFP modules temperature through MTMP register. Attempt to access this register on systems equipped with the this kind of silicon will cause initialization flow failure. Test for hardware resource capability is added in order to distinct between old and new silicon - old silicons do not have such capability. Fixes: 6a79507c ("mlxsw: core: Extend thermal module with per QSFP module thermal zones") Fixes: 5c42eaa0 ("mlxsw: core: Extend hwmon interface with QSFP module temperature attributes") Reported-by: NJiri Pirko <jiri@mellanox.com> Signed-off-by: NVadim Pasternak <vadimp@mellanox.com> Signed-off-by: NIdo Schimmel <idosch@mellanox.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 06 5月, 2019 4 次提交
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由 Geert Uytterhoeven 提交于
The THERMAL configuration option was changed from tristate to bool, but a dependency on THERMAL=m was forgotten, leading to a warning when running "make savedefconfig": boolean symbol THERMAL tested for 'm'? test forced to 'n' Fixes: be33e4fbbea581ea ("thermal/drivers/core: Remove the module Kconfig's option") Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Acked-by: NDaniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: NIdo Schimmel <idosch@mellanox.com> Reviewed-by: NKrzysztof Kozlowski <krzk@kernel.org> Signed-off-by: NZhang Rui <rui.zhang@intel.com>
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由 Jiri Pirko 提交于
Allow user to enable loopback feature for individual ports using ethtool. Signed-off-by: NJiri Pirko <jiri@mellanox.com> Signed-off-by: NIdo Schimmel <idosch@mellanox.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Jiri Pirko 提交于
The PPLR register allows configuration of the port's loopback mode. Signed-off-by: NJiri Pirko <jiri@mellanox.com> Signed-off-by: NIdo Schimmel <idosch@mellanox.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Pieter Jansen van Vuuren 提交于
Updates the Mellanox spectrum driver to use the newer intermediate representation for flow actions in matchall offloads. Signed-off-by: NPieter Jansen van Vuuren <pieter.jansenvanvuuren@netronome.com> Reviewed-by: NJakub Kicinski <jakub.kicinski@netronome.com> Acked-by: NJiri Pirko <jiri@mellanox.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 04 5月, 2019 3 次提交
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由 Shalom Toledo 提交于
When splitting a port, different local ports need to be mapped on different systems. For example: SN3700 (local_ports_in_2x=2): * Without split: front panel 1 --> local port 1 front panel 2 --> local port 5 * Split to 2: front panel 1s0 --> local port 1 front panel 1s1 --> local port 3 front panel 2 --> local port 5 SN3800 (local_ports_in_2x=1): * Without split: front panel 1 --> local port 1 front panel 2 --> local port 3 * Split to 2: front panel 1s0 --> local port 1 front panel 1s1 --> local port 2 front panel 2 --> local port 3 The local_ports_in_{1x, 2x} resources provide the offsets from the base local ports according to which the new local ports can be calculated. Signed-off-by: NShalom Toledo <shalomt@mellanox.com> Acked-by: NJiri Pirko <jiri@mellanox.com> Signed-off-by: NIdo Schimmel <idosch@mellanox.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Shalom Toledo 提交于
Since the number of local ports in 4x changed between SPC and SPC-2, firmware expose new resources that the driver can query. Signed-off-by: NShalom Toledo <shalomt@mellanox.com> Signed-off-by: NIdo Schimmel <idosch@mellanox.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Ido Schimmel 提交于
The new version supports two features that are required by upcoming changes in the driver: * Querying of new resources allowing port split into two ports on Spectrum-2 systems * Querying of number of gearboxes on supported systems such as SN3800 Signed-off-by: NIdo Schimmel <idosch@mellanox.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 24 4月, 2019 1 次提交
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由 David Ahern 提交于
mlxsw currently does not support v6 gateways with v4 routes. Commit 19a9d136 ("ipv4: Flag fib_info with a fib_nh using IPv6 gateway") prevents a route from being added, but nothing stops the replace or append. Add a catch for them too. $ ip ro add 172.16.2.0/24 via 10.99.1.2 $ ip ro replace 172.16.2.0/24 via inet6 fe80::202:ff:fe00:b dev swp1s0 Error: mlxsw_spectrum: IPv6 gateway with IPv4 route is not supported. $ ip ro append 172.16.2.0/24 via inet6 fe80::202:ff:fe00:b dev swp1s0 Error: mlxsw_spectrum: IPv6 gateway with IPv4 route is not supported. Signed-off-by: NDavid Ahern <dsahern@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 23 4月, 2019 6 次提交
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由 Ido Schimmel 提交于
Switch the CPU port to use the new dedicated egress pool instead the previously used egress pool which was shared with normal front panel ports. Add per-port quotas for the amount of traffic that can be buffered for the CPU port and also adjust the per-{port, TC} quotas. Signed-off-by: NIdo Schimmel <idosch@mellanox.com> Acked-by: NJiri Pirko <jiri@mellanox.com> Reviewed-by: NPetr Machata <petrm@mellanox.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Ido Schimmel 提交于
The CPU port is used to transmit traffic that is trapped to the host CPU. It is therefore irrelevant to define ingress quota for it. Add a 'skip_ingress' argument to the function tasked with configuring per-port quotas, so that ingress quotas could be skipped in case the passed local port is the CPU port. Signed-off-by: NIdo Schimmel <idosch@mellanox.com> Reviewed-by: NPetr Machata <petrm@mellanox.com> Acked-by: NJiri Pirko <jiri@mellanox.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Ido Schimmel 提交于
The function is used to set the per-port shared buffer quotas. Currently, these quotas are only set for front panel ports, but a subsequent patch will configure these quotas for the CPU port as well. The configuration required for the CPU port is a bit different than that of the front panel ports, so split the business logic into a separate function which will be called with different parameters for the CPU port. No functional changes intended. Signed-off-by: NIdo Schimmel <idosch@mellanox.com> Reviewed-by: NPetr Machata <petrm@mellanox.com> Acked-by: NJiri Pirko <jiri@mellanox.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Ido Schimmel 提交于
Use the new ingress pool that was added in the previous patch for control packets (e.g., STP, LACP) that are trapped to the CPU. The previous management pool is no longer necessary and therefore its size is set to 0. The maximum quota for traffic towards the CPU is increased to 50% of the free space in the new ingress pool and therefore the reserved space is reduced by half, to 10KB - in both the shared and headroom buffer. This allows for more efficient utilization of the shared buffer as reserved space cannot be used for other purposes. Signed-off-by: NIdo Schimmel <idosch@mellanox.com> Acked-by: NJiri Pirko <jiri@mellanox.com> Reviewed-by: NPetr Machata <petrm@mellanox.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Ido Schimmel 提交于
Packets that are trapped to the CPU are transmitted through the CPU port to the attached host. The CPU port is therefore like any other port and needs to have shared buffer configuration. The maximum quotas configured for the CPU are provided using dynamic threshold and cannot be changed by the user. In order to make sure that these thresholds are always valid, the configuration of the threshold type of these pools is forbidden. Signed-off-by: NIdo Schimmel <idosch@mellanox.com> Reviewed-by: NPetr Machata <petrm@mellanox.com> Acked-by: NJiri Pirko <jiri@mellanox.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Ido Schimmel 提交于
The code currently assumes that ingress pools have lower indices than egress pools. This makes it impossible to add more ingress pools without breaking user configuration that relies on a certain pool index to correspond to an egress pool. Remove such assumptions from the code, so that more ingress pools could be added by subsequent patches. Signed-off-by: NIdo Schimmel <idosch@mellanox.com> Reviewed-by: NPetr Machata <petrm@mellanox.com> Acked-by: NJiri Pirko <jiri@mellanox.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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