- 03 7月, 2017 4 次提交
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由 Arvind Yadav 提交于
Previously, we tried to clear interrupt requests by clearing bits in the PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI and PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN registers. But per the TRM, these fields are RW1C, so we must *set* bits to clear the interrupt bits. Fixes: 47ff3de9 ("PCI: dra7xx: Add TI DRA7xx PCIe driver") Signed-off-by: NArvind Yadav <arvind.yadav.cs@gmail.com> [bhelgaas: changelog] Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NKishon Vijay Abraham I <kishon@ti.com>
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由 Peter Robinson 提交于
The PCI controller attached to a SoC isn't much use if the core SoC isn't enabled, unless of course it's compile testing, so add appropriate dependency. Signed-off-by: NPeter Robinson <pbrobinson@gmail.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NKishon Vijay Abraham I <kishon@ti.com>
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由 Lorenzo Pieralisi 提交于
Since, through struct pci_host_bridge.map/swizzle_irq hooks, IRQs are now allocated in the pci_assign_irq() callback automatically, PCI host bridge drivers can stop relying on pci_fixup_irqs() for IRQ allocation. Drop pci_fixup_irqs() usage from PCI designware host bridge driver. Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Joao Pinto <Joao.Pinto@synopsys.com>
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由 Lorenzo Pieralisi 提交于
The introduction of pci_scan_root_bus_bridge() provides a PCI core API to scan a PCI root bus backed by an already initialized struct pci_host_bridge object, which simplifies the bus scan interface and makes the PCI scan root bus interface easier to generalize as members are added to the struct pci_host_bridge. Convert PCI designware host code to pci_scan_root_bus_bridge() to improve the PCI root bus scanning interface. Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Joao Pinto <Joao.Pinto@synopsys.com>
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- 28 4月, 2017 5 次提交
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由 Brian Norris 提交于
Many PCI host controller drivers aren't prepared to have their devices unbound from them forcefully (e.g., through /sys/.../<driver>/unbind), as they don't provide any driver .remove callback, where they'd detach the root bus, release resources, etc. Keeping the driver built in (i.e., not a loadable module) is not enough; and providing no .remove callback just means we don't do any teardown. To rule out the possibility of unbinding a device via sysfs, we need to set the ".suppress_bind_attrs" field. I found the suspect drivers via the following search: git grep -l platform_driver $(git grep -L -e '\.remove' -e suppress_bind_attrs drivers/pci/) Then I inspected them to ensure that (a) they set up a PCI bus in their probe() and (b) they don't have a remove() callback for undoing the setup Suggested-by: NBjorn Helgaas <helgaas@kernel.org> Signed-off-by: NBrian Norris <briannorris@chromium.org> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Kishon Vijay Abraham I 提交于
According to errata i870, access to the PCIe slave port that are not 32-bit aligned will result in incorrect mapping to TLP Address and Byte enable fields. Accessing non 32-bit aligned data causes incorrect data in the target buffer if memcpy is used. Implement the workaround for this errata here. Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Kishon Vijay Abraham I 提交于
The PCIe controller integrated in dra7xx SoCs is capable of operating in endpoint mode. Add endpoint mode support to dra7xx driver. Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Kishon Vijay Abraham I 提交于
No functional change. Split dra7xx_pcie_enable_interrupts() into dra7xx_pcie_enable_wrapper_interrupts() and dra7xx_pcie_enable_msi_interrupts() so that wrapper interrupts and MSI interrupts can be enabled independently. This is in preparation for adding EP mode support to dra7xx driver since EP mode doesn't have to enable msi_interrupts. Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Kishon Vijay Abraham I 提交于
Add endpoint mode support to designware driver. This uses the EP Core layer introduced recently to add endpoint mode support. *Any* function driver can now use this designware device in order to achieve the EP functionality. Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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- 26 4月, 2017 1 次提交
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由 Colin Ian King 提交于
Trivial fix to spelling mistake in dev_err message Signed-off-by: NColin Ian King <colin.king@canonical.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NRichard Zhu <hongxing.Zhu@nxp.com>
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- 25 4月, 2017 7 次提交
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由 Lorenzo Pieralisi 提交于
PCI configuration space should be mapped with a memory region type that generates on the CPU host bus non-posted write transations. Update the driver to use the devm_pci_remap_cfg* interface to make sure the correct memory mappings for PCI configuration space are used. Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Cc: Murali Karicheri <m-karicheri2@ti.com>
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由 Lorenzo Pieralisi 提交于
PCI configuration space should be mapped with a memory region type that generates on the CPU host bus non-posted write transations. Update the driver to use the devm_pci_remap_cfg* interface to make sure the correct memory mappings for PCI configuration space are used. Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Cc: Mingkai Hu <mingkai.hu@freescale.com> Cc: Minghuan Lian <minghuan.Lian@freescale.com> Cc: Roy Zang <tie-fei.zang@freescale.com>
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由 Lorenzo Pieralisi 提交于
PCI configuration space should be mapped with a memory region type that generates on the CPU host bus non-posted write transations. Update the driver to use the devm_pci_remap_cfg* interface to make sure the correct memory mappings for PCI configuration space are used. Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: NGabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Cc: Zhou Wang <wangzhou1@hisilicon.com>
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由 Lorenzo Pieralisi 提交于
PCI configuration space should be mapped with a memory region type that generates on the CPU host bus non-posted write transations. Update the driver to use the devm_pci_remap_cfg* interface to make sure the correct memory mappings for PCI configuration space are used. Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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由 Lorenzo Pieralisi 提交于
PCI configuration space should be mapped with a memory region type that generates on the CPU host bus non-posted write transations. Update the driver to use the devm_pci_remap_cfg* interface to make sure the correct memory mappings for PCI configuration space are used. Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Joao Pinto <Joao.Pinto@synopsys.com>
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由 Lorenzo Pieralisi 提交于
PCI configuration space should be mapped with a memory region type that generates on the CPU host bus non-posted write transations. Update the driver to use the devm_pci_remap_cfg* interface to make sure the correct memory mappings for PCI configuration space are used. Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Cc: Stanimir Varbanov <svarbanov@mm-sol.com>
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由 Lorenzo Pieralisi 提交于
PCI configuration space should be mapped with a memory region type that generate on the CPU host bus non-posted write transations. Update the driver to use the devm_pci_remap_cfg* interface to make sure the correct memory mappings for PCI configuration space are used. Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Cc: Pratyush Anand <pratyush.anand@gmail.com>
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- 12 4月, 2017 1 次提交
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由 Dongdong Liu 提交于
The "hisilicon,pcie-almost-ecam" binding goes against the usual DT conventions, and is non-sensical in that it describes the IP based on what it isn't. Fix the DT binding with "hisilicon,hip06-pcie-ecam" and "hisilicon,hip07-pcie-ecam". Signed-off-by: NMark Rutland <mark.rutland@arm.com> Signed-off-by: NDongdong Liu <liudongdong3@huawei.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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- 05 4月, 2017 4 次提交
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由 Andrey Smirnov 提交于
Save a bit of time and avoid going through link speed change procedure in configuration where link max speed is limited to Gen1 in DT. Signed-off-by: NAndrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NLucas Stach <l.stach@pengutronix.de> Cc: yurovsky@gmail.com Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Dong Aisheng <dongas86@gmail.com> Cc: linux-arm-kernel@lists.infradead.org
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由 Andrey Smirnov 提交于
As can be seen from [1]: "...the different behavior between iMX6Q PCIe and iMX7D PCIe maybe caused by the different controller version. Regarding to the DOC description, the DIRECT_SPEED_CHANGE should be cleared after the speed change from GEN1 to GEN2. Unfortunately, when GEN1 device is used, the behavior is not documented. So, IC design guys run the simulation and find out the following behaviors: 1. DIRECT_SPEED_CHANGE will be cleared in 7D after speed change from GEN1 to GEN2. This matches doc’s description 2. set MAX link speed(PCIE_CAP_TARGET_LINK_SPEED=0x01) as GEN1 and re-run the simulation, DIRECT_SPEED_CHANGE will not be cleared; remain as 1, this matches your result, but function test is passed, so this bit should not affect the normal PCIe function." imx6_pcie_wait_for_speed_change() will report false failures for Gen1 -> Gen1 speed transition, so avoid doing that check and just rely on imx6_pcie_wait_for_link() only. [1] https://community.nxp.com/message/867943Signed-off-by: NAndrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NLucas Stach <l.stach@pengutronix.de> Cc: yurovsky@gmail.com Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Dong Aisheng <dongas86@gmail.com> Cc: linux-arm-kernel@lists.infradead.org
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由 Andrey Smirnov 提交于
Some designs implement reset GPIO via a GPIO expander connected to a peripheral bus. One such example would be i.MX7 Sabre board where said GPIO is provided by SPI shift register connected to a bitbanged SPI bus. To support such designs, allow reset GPIO request to defer probing of the driver. Signed-off-by: NAndrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NLucas Stach <l.stach@pengutronix.de> Cc: yurovsky@gmail.com Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Dong Aisheng <dongas86@gmail.com> Cc: linux-arm-kernel@lists.infradead.org
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由 Andrey Smirnov 提交于
Add various bits of code needed to support i.MX7D variant of the IP. Signed-off-by: NAndrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NLucas Stach <l.stach@pengutronix.de> Acked-by: NLee Jones <lee.jones@linaro.org> Acked-by: NRob Herring <robh@kernel.org> Cc: yurovsky@gmail.com Cc: Mark Rutland <mark.rutland@arm.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Dong Aisheng <dongas86@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org
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- 04 4月, 2017 11 次提交
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由 Keerthy 提交于
Currently devm_request_irq() is being called before base, PCI fields of dra7xx_pcie structure are populated. It is called even before pm_runtime_enable() and pm_runtime_get_sync() are called. This will lead to exceptions if in case an interrupt is triggered before the all of the above are done. Hence push the devm_request_irq() call to the end of the probe. Signed-off-by: NKeerthy <j-keerthy@ti.com> Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Kishon Vijay Abraham I 提交于
No functional change. Rename dw_pcie_writel_unroll/dw_pcie_readl_unroll to dw_pcie_writel_ob_unroll/dw_pcie_readl_ob_unroll respectively as these functions are used to perform only outbound configurations. Also move these _unroll configurations to a separate function. Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Kishon Vijay Abraham I 提交于
Previously dbi accessors can be used to access data of size 4 bytes. But there might be situations (like accessing MSI_MESSAGE_CONTROL in order to set/get the number of required MSI interrupts in EP mode) where dbi accessors must be used to access data of size 2. This is in preparation for adding endpoint mode support to designware driver. Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NNiklas Cassel <niklas.cassel@axis.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Joao Pinto <Joao.Pinto@synopsys.com>
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由 Kishon Vijay Abraham I 提交于
dwc has 2 dbi address space labeled dbics and dbics2. The existing helper to access dbi address space can access only dbics. However dbics2 has to be accessed for programming the BAR registers in the case of EP mode. This is in preparation for adding EP mode support to dwc driver. Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NNiklas Cassel <niklas.cassel@axis.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Joao Pinto <Joao.Pinto@synopsys.com>
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由 Kishon Vijay Abraham I 提交于
Populate cpu_addr_fixup ops to extract the least 28 bits of the corresponding CPU address. Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NNiklas Cassel <niklas.cassel@axis.com> Acked-by: NJoao Pinto <jpinto@synopsys.com>
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由 Kishon Vijay Abraham I 提交于
Populate cpu_addr_fixup ops to extract the least 28 bits of the corresponding CPU address. Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NJoao Pinto <jpinto@synopsys.com>
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由 Kishon Vijay Abraham I 提交于
Some platforms (like dra7xx) require only the least 28 bits of the corresponding 32 bit CPU address to be programmed in the address translation unit. This modified address is stored in io_base/mem_base/ cfg0_base/cfg1_base in dra7xx_pcie_host_init(). While this is okay for host mode where the address range is fixed, device mode requires different addresses to be programmed based on the host buffer address. Add a new ops to get the least 28 bits of the corresponding 32 bit CPU address and invoke it before programming the address translation unit. Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NJoao Pinto <jpinto@synopsys.com>
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由 Dan Carpenter 提交于
The bug is that "val" is unsigned long but we only initialize 32 bits of it. Then we test "if (val)" and that might be true not because we set the bits but because some were never initialized. Fixes: f342d940 ("PCI: exynos: Add support for MSI") Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Bjorn Helgaas 提交于
Use "continue" to skip rest of the loop when possible to save an indent level. No functional change intended. Suggested-by: Nwalter harms <wharms@bfs.de> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Niklas Cassel 提交于
Fix a crash from dereferencing a NULL dw_pcie_ops pointer. For example, on ARTPEC-6: Unable to handle kernel NULL pointer dereference at virtual address 00000004 pgd = c0204000 [00000004] *pgd=00000000 Internal error: Oops: 5 [#1] SMP ARM Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.11.0-rc3-next-20170321 #1 Hardware name: Axis ARTPEC-6 Platform task: db098000 task.stack: db096000 PC is at dw_pcie_writel_dbi+0x2c/0xd0 Prior to 442ec4c0 ("PCI: dwc: all: Split struct pcie_port into host-only and core structures"), every driver had a struct pcie_host_ops with function pointers, typically used as: if (pp->ops->readl_rc) return pp->ops->readl_rc(...); 442ec4c0 split struct pcie_host_ops into two pieces: struct dw_pcie_host_ops and struct dw_pcie_ops, so the above became: if (pci->ops->readl_dbi) return pci->ops->readl_dbi(...); But pcie-artpec6.c and pcie-designware-plat.c don't need the dw_pcie_ops pointers and didn't supply a pci->ops struct, which leads to NULL pointer dereferences. Supply an empty struct dw_pcie_ops to avoid the NULL pointer dereferences. [bhelgaas: changelog] Fixes: 442ec4c0 ("PCI: dwc: all: Split struct pcie_port into host-only and core structures") Signed-off-by: NNiklas Cassel <niklas.cassel@axis.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NKishon Vijay Abraham I <kishon@ti.com> Acked-by: NJoao Pinto <jpinto@synopsys.com>
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由 Arnd Bergmann 提交于
Without PCI_HOST_COMMON support enabled, we get a link error: drivers/pci/dwc/built-in.o: In function `hisi_pcie_map_bus': pcie-hisi.c:(.text+0x8860): undefined reference to `pci_ecam_map_bus' drivers/pci/dwc/built-in.o: In function `hisi_pcie_almost_ecam_probe': pcie-hisi.c:(.text+0x88b4): undefined reference to `pci_host_common_probe' Add an explicit 'select', as the other users have. Signed-off-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NJingoo Han <jingoohan1@gmail.com>
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- 08 3月, 2017 1 次提交
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由 Jaehoon Chung 提交于
Even when using the PHY framework, we need the elbi_base. Before this patch, we didn't initialize elbi_base, which caused NULL pointer dereferences later. Fixes: e7cd7ef5 ("PCI: exynos: Support the PHY generic framework") Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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- 25 2月, 2017 1 次提交
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由 Guenter Roeck 提交于
Fix the following crash, seen in dwc/pci-imx6. Unable to handle kernel NULL pointer dereference at virtual address 00000070 pgd = c0004000 [00000070] *pgd=00000000 Internal error: Oops: 805 [#1] SMP ARM Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.10.0-09686-g9e314890 #1 Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree) task: cb850000 task.stack: cb84e000 PC is at imx6_pcie_probe+0x2f4/0x414 ... While at it, fix the same problem in various drivers instead of waiting for individual crash reports. The change in the imx6 driver was tested with qemu. The changes in other drivers are based on code inspection and have been compile tested only. Fixes: 442ec4c0 ("PCI: dwc: all: Split struct pcie_port into host-only and core structures") Signed-off-by: NGuenter Roeck <linux@roeck-us.net> Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> # designware-plat Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NKishon Vijay Abraham I <kishon@ti.com>
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- 22 2月, 2017 5 次提交
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由 Kishon Vijay Abraham I 提交于
CONFIG_PCI is used to enable host mode PCI. In preparation for adding endpoint mode support to designware driver, remove the dependency of designware on CONFIG_PCI and make only the host-specific part depend on CONFIG_PCI. Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Kishon Vijay Abraham I 提交于
Now that PCI designware host has a separate file, add a new PCIE_DW_HOST config symbol to select the host-only driver. This will enable to independently select host support and endpoint support (when it's added). Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Kishon Vijay Abraham I 提交于
Split pcie-designware.c into pcie-designware-host.c that contains the host specific parts of the driver and pcie-designware.c that contains the parts used by both host driver and endpoint driver. Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Kishon Vijay Abraham I 提交于
No functional change. Fix all checkpatch warnings and check errors in pcie-designware.c Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-By: NJoao Pinto <jpinto@synopsys.com>
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由 Kishon Vijay Abraham I 提交于
The "num-lanes" DT property is parsed in dw_pcie_host_init(). However num-lanes is applicable to both root complex mode and endpoint mode. As a first step, move the parsing of this property outside dw_pcie_host_init(). This is in preparation for splitting pcie-designware.c to pcie-designware.c and pcie-designware-host.c Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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