- 03 8月, 2013 7 次提交
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由 Yadwinder Singh Brar 提交于
This patch defines a common rate_table which will contain recommended p, m, s, k values for supported rates that needs to be changed for changing corresponding PLL's rate. Reviewed-by: NDoug Anderson <dianders@chromium.org> Signed-off-by: NYadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Yadwinder Singh Brar 提交于
This patch removes samsung_clk_register_pll35xx() and samsung_clk_register_pll36xx() registaration functions as users migrated to new samsung_clk_register_pll(). Signed-off-by: NYadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Yadwinder Singh Brar 提交于
This patch migrates exynos5420 pll registeration to use common samsung_clk_register_pll() by intialising table of PLLs and adding PLLs to unique id list of clocks. Signed-off-by: NYadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: NVikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Yadwinder Singh Brar 提交于
This patch migrates exynos4 pll registeration to use common samsung_clk_register_pll() by intialising table of PLLs. Signed-off-by: NYadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: NVikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Yadwinder Singh Brar 提交于
This patch migrates exynos5250 pll registeration to use common samsung_clk_register_pll() by intialising table of PLLs and adding PLLs to unique id list of clocks. Signed-off-by: NYadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: NVikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Yadwinder Singh Brar 提交于
This patch defines a common samsung_clk_register_pll() Since pll2550 & pll35xx and pll2650 & pll36xx have exactly same clk ops implementation, added pll2550 and pll2650 also. Signed-off-by: NYadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Yadwinder Singh Brar 提交于
This patch unifies clk strutures used for PLL35xx & PLL36xx and adding an extra member lock_reg, so that common code can be factored out. Reviewed-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NYadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 31 7月, 2013 3 次提交
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由 Sachin Kamat 提交于
Added clock entries for thermal management unit (TMU) for Exynos4 SoCs. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Rahul Sharma 提交于
hdmi driver needs hdmiphy clock which is one of the parent for hdmi mux clock. This is required while changing the parent of mux clock. Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Rahul Sharma 提交于
hdmi driver needs to change the parent of hdmi clock frequently between pixel clock and hdmiphy clock. hdmiphy is not stable after power on and for a short interval while changing the phy configuration. For this duration pixel clock is used to clock hdmi. This patch is exposing the mux for changing parent. Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 30 7月, 2013 1 次提交
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由 Sachin Kamat 提交于
Adds gate clock for G2D IP for Exynos5250 SoC. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 26 7月, 2013 6 次提交
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由 Sachin Kamat 提交于
exynos_audss_clk_init() is used only in this file. Make it static. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Acked-by: NKukjin Kim <kgene.kim@samsung.com> Reviewed-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Sachin Kamat 提交于
Symbols referenced only in this file are made static. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Acked-by: NKukjin Kim <kgene.kim@samsung.com> Reviewed-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Sachin Kamat 提交于
Symbols referenced only in this file are made static. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Acked-by: NKukjin Kim <kgene.kim@samsung.com> Reviewed-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Sachin Kamat 提交于
Symbols referenced only in this file are made static. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Acked-by: NKukjin Kim <kgene.kim@samsung.com> Reviewed-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Sachin Kamat 提交于
Subsequent to the cleanup in commit 3c70348c ("ARM: EXYNOS: Remove legacy timer initialization code"), this function has no more users. Hence remove it. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Reviewed-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Sachin Kamat 提交于
Symbols referenced only in this file are made static. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Reviewed-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 23 6月, 2013 2 次提交
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由 Tushar Behera 提交于
cpufreq driver for EXYNOS4 based SoCs are not platform drivers, hence we cannot currently pass the clock names through a device tree node. Instead, we need to make them available through a global alias. Clock alias modifications for EXYNOS4 specific clocks are as below. Alias for clock 'arm_clk' is 'armclk'. Alias for clock 'mout_apll' is 'mout_apll'. Alias for clock 'mout_core' is 'moutcore'. For EXYNOS4210, alias for clock 'sclk_mpll' is 'mout_mpll'. For EXYNOS4412, alias for clock 'mout_mpll_user_c' is 'mout_mpll'. Some of the clock aliases are newly defined and some are fixed up. While at it, also modify the debug messages to print the clock values appropriately. Signed-off-by: NTushar Behera <tushar.behera@linaro.org> Reviewed-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Tushar Behera 提交于
Cpufreq driver for some Samsung platforms have not yet been designed as a platform driver, thereby they can only access clocks with an alias name. For EXYNOS4210, one such clock also requires a flag to be set, hence there is a need to create another macro that can handle both flag and alias. Signed-off-by: NTushar Behera <tushar.behera@linaro.org> Reviewed-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 19 6月, 2013 3 次提交
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由 Chander Kashyap 提交于
The EXYNOS5420 clocks are statically listed and registered using the Samsung specific common clock helper functions. Signed-off-by: NChander Kashyap <chander.kashyap@linaro.org> Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org> Reviewed-by: NTomasz Figa <t.figa@samsung.com> Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Padmavathi Venna 提交于
This patch adds enum entries for div_i2s1 and div_i2s2 which are required for i2s1 and i2s2 controllers. Signed-off-by: NPadmavathi Venna <padma.v@samsung.com> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Padmavathi Venna 提交于
Audio subsystem is introduced in s5pv210 and exynos platforms. This has seperate clock controller which can control i2s0 and pcm0 clocks. This patch registers the audio subsystem clocks with the common clock framework on Exynos family. Signed-off-by: NPadmavathi Venna <padma.v@samsung.com> Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: NDoug Anderson <dianders@chromium.org> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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- 12 6月, 2013 3 次提交
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由 Tushar Behera 提交于
Currently 'pmu' clock is not handled by any of the drivers. Also before the introduction of CCF, this clock was not defined, hence was left enabled always. When this clock is disabled, software reset register becomes inaccessible and system reboot doesn't work. Upon restoring the default behaviour, system reboot starts working. Signed-off-by: NTushar Behera <tushar.behera@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Sachin Kamat 提交于
Add G2D clocks for Exynos4x12 SoC and sclk_fimg2d required by G2D IP. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Cc: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Doug Anderson 提交于
The KDIV value is often listed as unsigned but it needs to be treated as a 16-bit signed value when using it in calculations. Fix our rate recalculation to do this correctly. Before doing this, I tried setting EPLL on exynos5250 to: rate, m, p, s, k = 80000000, 107, 2, 4, 43691 This rate is exactly from the table in the exynos5250 user manual. I read this back as 80750003 with: cat /sys/kernel/debug/clk/fin_pll/fout_epll/clk_rate After this patch, it reads back as 80000003 Signed-off-by: NDoug Anderson <dianders@chromium.org> Acked-by: NKukjin Kim <kgene.kim@samsung.com> Reviewed-by: NVikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 11 6月, 2013 2 次提交
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由 Tushar Behera 提交于
'mout_mpll' is added the list of parent clocks for 'mout_cpu'. 'mout_mpll' is an alias to the clock 'sclk_mpll'. Hence 'sclk_mpll' should be added to the list of parent clocks. This results in an error when cpufreq driver for EXYNOS5250 tries to set 'mout_mpll' as a parent for 'mout_cpu'. clk_set_parent: clk sclk_mpll can not be parent of clk mout_cpu Signed-off-by: NTushar Behera <tushar.behera@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Tushar Behera 提交于
cpufreq driver for EXYNOS5250 is not a platform driver, hence we cannot currently pass the clock names through a device tree node. Instead, we need to make them available through a global alias. cpufreq driver for EXYNOS5250 requires four clocks - 'armclk', 'mout_cpu', 'mout_mpll' and 'mout_apll'. 'armclk' has already been defined with an alias, 'mout_cpu', 'mout_mpll' and 'mout_apll' are now defined with an alias. Signed-off-by: NTushar Behera <tushar.behera@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 30 5月, 2013 3 次提交
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由 Tushar Behera 提交于
'mout_mpll' is added the list of parent clocks for 'mout_cpu'. 'mout_mpll' is an alias to the clock 'sclk_mpll'. Hence 'sclk_mpll' should be added to the list of parent clocks. This results in an error when cpufreq driver for EXYNOS5250 tries to set 'mout_mpll' as a parent for 'mout_cpu'. clk_set_parent: clk sclk_mpll can not be parent of clk mout_cpu Signed-off-by: NTushar Behera <tushar.behera@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Tushar Behera 提交于
cpufreq driver for EXYNOS5250 is not a platform driver, hence we cannot currently pass the clock names through a device tree node. Instead, we need to make them available through a global alias. cpufreq driver for EXYNOS5250 requires four clocks - 'armclk', 'mout_cpu', 'mout_mpll' and 'mout_apll'. 'armclk' has already been defined with an alias, 'mout_cpu', 'mout_mpll' and 'mout_apll' are now defined with an alias. Signed-off-by: NTushar Behera <tushar.behera@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Sylwester Nawrocki 提交于
Currently no driver *) handles the sysreg clock, with an assumption that this clock is always left in its default state (enabled). Before commit 6e6aac75 ARM: EXYNOS: Migrate clock support to common clock framework the sysreg clock was not even defined and hence wasn't handled explicitly in the kernel. To restore the previous behaviour disable masking the sysreg clock off in the clock core by default. *) Except the Exynos4x12 FIMC-IS driver, which will be modified to not touch the sysreg clock. Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 24 4月, 2013 1 次提交
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由 Tushar Behera 提交于
commit 688f7d8c ("clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3}") incorrectly sets the divider for sclk_mmc{0,1,2,3} to fix the wrong clock value. Though this fixed issue with Arndale, it created regressions for other boards like Snow. On Exynos5250, sclk_mmc<n> is generated like below (as per the clock names in drivers/clk/samsung/clk-exynos5250.c) mout_group1_p ==> mout_mmc<n> ==> div_mmc<n> ==> div_mmc_pre<n> => sclk_mmc<n> Earlier div_mmc<n> was set as the parent for sclk_mmc<n>, hence div_mmc_pre<n> was not getting referred in kernel code and depending on its value set during preboot, sclk_mmc<n> value was different for various boards. Setting the correct clock generation path should fix the issues reported in above referenced commit. The changes committed during the earlier patch has also been reverted here. Reported-by: NDoug Anderson <dianders@chromium.org> Signed-off-by: NTushar Behera <tushar.behera@linaro.org> Tested-by: NDoug Anderson <dianders@chromium.org> Acked-by: NKukjin Kim <kgene.kim@samsung.com> Signed-off-by: NOlof Johansson <olof@lixom.net>
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- 20 4月, 2013 1 次提交
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由 Arnd Bergmann 提交于
The new common clock drivers for exynos are using compile time constants and soc_is_exynos* macros to provide backwards compatibility for pre-DT systems, which is not possible with multiplatform kernels. This moves all the necessary information back into platform code and removes the mach/* header inclusions. Signed-off-by: NArnd Bergmann <arnd@arndb.de> Cc: Mike Turquette <mturquette@linaro.org>
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- 08 4月, 2013 3 次提交
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由 Tushar Behera 提交于
In legacy setup, sclk_mmc{0,1,2,3} used PRE_RATIO bit-field (8-bit wide) instead of RATIO bit-field (4-bit wide) for dividing clock rate. With current common clock setup, we are using RATIO bit-field which is creating FIFO read errors while accessing eMMC. Changing over to use PRE_RATIO bit-field fixes this issue. dwmmc_exynos 12200000.dwmmc0: data FIFO error (status=00008020) mmcblk0: error -5 transferring data, sector 1, nr 7, cmd response 0x900, card status 0x0 end_request: I/O error, dev mmcblk0, sector 1 Signed-off-by: NTushar Behera <tushar.behera@linaro.org> CC: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Sylwester Nawrocki 提交于
This patch adds clock indexes for ACLK_DIV0, ACLK_DIV1, ACLK_400_MCUISP, ACLK_MCUISP_DIV0, ACLK_MCUISP_DIV1, DIVACLK_400_MCUISP and DIVACLK_200 so these clocks are available to the consumers (Exynos4x12 FIMC-IS subsystem). While at it, indentation of the mux clocks table is corrected. Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Sachin Kamat 提交于
Fixes the below compilation error during non-dt build. drivers/clk/samsung/clk.c: In function 'samsung_clk_of_register_fixed_ext': drivers/clk/samsung/clk.c:252:2: error: implicit declaration of function 'for_each_matching_node_and_match' [-Werror=implicit-function-declaration] drivers/clk/samsung/clk.c:252:60: error: expected ';' before '{' token Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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- 04 4月, 2013 5 次提交
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由 Leela Krishna Amudala 提交于
Add gate clocks for fimd, mie, dsim, dp, mixer and hdmi. Register it to common clock framework. Signed-off-by: NLeela Krishna Amudala <l.krishna@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Tomasz Figa 提交于
This patch extends suspend/resume support for SoC-specific registers to handle differences in register sets on particular SoCs. Signed-off-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> Reviewed-by: NThomas Abraham <thomas.abraham@linaro.org> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Tomasz Figa 提交于
This patch adds missing clock control registers to the list of registers that should be saved across system suspend. Signed-off-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> Reviewed-by: NThomas Abraham <thomas.abraham@linaro.org> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Tomasz Figa 提交于
This register is present on all Exynos4 SoCs and so the prefix is misleading. Signed-off-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> Reviewed-by: NThomas Abraham <thomas.abraham@linaro.org> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Tomasz Figa 提交于
This definition is specific for Exynos4210 (which has another location than the same register on Exynos4x12 SoCs) and so needs appropriate prefix. Signed-off-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> Reviewed-by: NThomas Abraham <thomas.abraham@linaro.org> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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