This reverts commit b403125d.

As reported by Chris, both commits
        b403125d "ARM: rockchip: fix undefined instruction of reset_ctrl_regs"
        0ea001d3 "ARM: rockchip: disable dapswjdp during suspend"
actually fix the same issue and b403125d is the older one, which got
superseded by 0ea001d3. Therefore revert the obsolete one again.
Reported-by: NChris Zhong <zyw@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Sometimes the debug module may not work well after resume, since it has
not been correctly reset when wakeup from suspend. That cause system
crash during reusme, and a 'undefined instruction' is displayed on the
console. Set the GRF_FORCE_JTAG bit of RK3288_GRF_SOC_CON0 can ensure
that debug modul is reset. And we can change the value of
RK3288_GRF_SOC_CON0 back when system resume.
Signed-off-by: NChris Zhong <zyw@rock-chips.com>
Tested-by: NCaesar Wang <wxt@rock-chips.com>
Reviewed-by: NDouglas Anderson <dianders@chromium.org>

According to discussions, there does not seem a better solution available.
Please also see the potential security implication described in the
comment inline in the code.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Reset dapswjdp is controlled by JTAG_TRSTN, if the iomux of this pin is
not "jtag_trstn". the AP would think this pin is always high, so it can
not reset before resume. When system resume, but the dapswjdp is not in
a default state, it may Access some illegal address, it cause system
crash during resume.
Let's disable this jtag function by clear the dapdeviceen bit, it
prohibit the dapswjdp to access memory and registers. This bit would
be enable in MASKROM, so we need clear it in suspend everytime.
Signed-off-by: NChris Zhong <zyw@rock-chips.com>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The watchdog clock should be disable in dw_wdt_suspend, but we set a
dummy clock to watchdog for rk3288. So the watchdog will continue to
work during suspend. And we switch the system clock to 32khz from 24Mhz,
during suspend, so the watchdog timer over count will increase to
755 times, about 12.5 hours, the original value is 60 seconds. So
watchdog will reset the system over a night,  but voltage are all
incorrect, then it hang on reset.
Signed-off-by: NChris Zhong <zyw@rock-chips.com>
Signed-off-by: NDaniel Kurtz <djkurtz@google.com>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Tested-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The register-default delay time for wait the 24MHz OSC stabilization as well
as PMU stabilization is 750ms, let's decrease them to a still safe 30ms.
Signed-off-by: NChris Zhong <zyw@rock-chips.com>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Tested-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

It's a basic version of suspend and resume for rockchip,
it only support RK3288 now.
Signed-off-by: NTony Xie <xxx@rock-chips.com>
Signed-off-by: NChris Zhong <zyw@rock-chips.com>
Tested-by: NDoug Anderson <dianders@chromium.org>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>