On bf518-ezbrd with DSA Ethernet switch enabled, on chip MAC is
connecting to phy at address 3.  If allowing the netdevice framework to
probe both 3 phys of the switch when registering MAC phy, phy at address
1 is checked for link active status other than phy at address 3.  If
connecting a cable to port 2 and leave port 1 open, link status in phy
2 and 3 are online, while that in phy 1 is offline.  So, the phy layer
sets wrong offline status to net device on port 3.  In this case, no data
can be transferred via ethernet port 2.
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The SPORT/UART driver doesn't use the secondary channel pins, so don't
try and request them thus keeping other drivers from using them.
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

These were only included because of the irq handling of the PLL funcs,
and those PLL funcs have been moved out into their own header now.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The defBF512.h header exists only to include defBF51x_base.h, and it is
the only place where defBF51x_base.h is included.  So move the contents
of the defBF51x_base.h header into the defBF512.h header.

Same situation for the other def/cdef pairs.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The main asm/blackfin.h header will pull in mach/blackfin.h to get
all the fun Blackfin defines.  So having any of the sub-mach headers
trying to include asm/blackfin.h makes no sense -- punt it.

The mach/blackfin.h header takes care of including the part-specific
def headers which in turn will include any other needed def file.
Similarly, it takes care of pulling in the part-specific cdef header.
So move this logic out of the blackfin.h when necessary.

Further, make sure the cdef headers do not waste time including the
def headers again.

Since all parts need the common def/cdef headers, move this logic
out of the part-specific headers and into the mach/blackfin.h file.

Finally, we need to split the BF539 def header since the BF538 does
not have MXVR and we don't want to expose those MMRs.

So now all parts should have the same behavior:
	mach/blackfin.h
		asm/def_LPBlackfin.h
		part-specific def.h
		if ! asm
			asm/cdef_LPBlackfin.h
			part-specific cdef.h
And the sub def/cdef headers only tail into what they need.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The array of pointers is never written, so constify it.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Use the same naming convention for DMA traffic MMRs (most were legacy
anyways) so we can avoid useless ifdef trees.

Same goes for MDMA names -- this actually allows us to undo a bunch of
ifdef redirects that existed for this purpose alone.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Each Blackfin port has been duplicating UART structures and defines when
there really is no need for it.  So start a new bfin_serial.h header to
unify all these pieces and give ourselves a fresh start.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Move all the pin settings out of the Kconfig and into the platform
resources (MII vs RMII).  This clean up also lets us push out the
phy settings so that board porters may control the layout.
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>
Acked-by: NDavid S. Miller <davem@davemloft.net>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

This board has a SSM2603 codec, so make sure we have the right resources
declared for it.
Signed-off-by: NBob Liu <lliubbo@gmail.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The RX/TX address is always the same regardless of the size of the access.
That means there is no dedicated "16bit" or "32bit" MMR.  Trying to use
these currently leads to compile errors.  So change everything to use the
right MMR define.
Signed-off-by: NBob Liu <lliubbo@gmail.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The num_chipselect field for on-chip Blackfin SPI buses is supposed to
be 1 larger than the number of actual CSs available.  This is because
the hardware starts counting at 1 and not 0.  There is a field for "CS0",
but it is marked as "reserved" everywhere.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Now that the common header defines everything and the SPI drivers are
using it, we can drop these duplicated global namespace polluters.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Rename h/w IRQ flags handling functions to be in line with what is expected for
the irq renaming patch.  This renames local_*_hw() to hard_local_*() using the
following perl command:

	perl -pi -e 's/local_irq_(restore|enable|disable)_hw/hard_local_irq_\1/ or s/local_irq_save_hw([_a-z]*)[(]flags[)]/flags = hard_local_irq_save\1()/' `find arch/blackfin/ -name "*.[ch]"`

and then fixing up asm/irqflags.h manually.

Additionally, arch/hard_local_save_flags() and arch/hard_local_irq_save() both
return the flags rather than passing it through the argument list.
Signed-off-by: NDavid Howells <dhowells@redhat.com>

Split the PLL control code from the Blackfin machine-specific cdef headers so
that the irqflags functions can be renamed without incurring a header loop.
Signed-off-by: NDavid Howells <dhowells@redhat.com>

The common bfin_sport.h header now has unified definitions of these, so
stop polluting the global namespace.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Avoid duplication and ugly global namespace pollution.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Avoid duplication and ugly global namespace pollution.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The standard short name for control is CTL and not CTRL.  Use TWI0_xxx
even on parts that only have one TWI bus to keep things simple.  Drop
all the cdef helpers since the bus driver takes care of everything.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Newer parts have optional Hysteresis/Schmitt Trigger options to help with
dirty signals.  So add some kconfig options for tuning this and enable it
by default for people.
Signed-off-by: NMichael Hennerich <michael.hennerich@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Random tabs instead of spaces, mixes of the two, and unicode spaces
instead of ascii spaces.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Even though the PH8 pin is only internal to the processor packaging, it
can be controlled like any other GPIO pin.  Now that we have a proper GPIO
define, we can fix the SPI0 CS4 define for the internal SPI flash.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

This is parallel to the existing P_DEFAULT_BOOT_SPI_CS, but in terms of
the GPIO value so it can be used with the normal gpio API.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

This patch provides infrastructure for MAC Wake-On-Lan and PHYINT use in
phylib.  New Interrupts added:

IRQ_MAC_PHYINT   /* PHY_INT Interrupt */
IRQ_MAC_MMCINT   /* MMC Counter Interrupt */
IRQ_MAC_RXFSINT  /* RX Frame-Status Interrupt */
IRQ_MAC_TXFSINT  /* TX Frame-Status Interrupt */
IRQ_MAC_WAKEDET  /* Wake-Up Interrupt */
IRQ_MAC_RXDMAERR /* RX DMA Direction Error Interrupt */
IRQ_MAC_TXDMAERR /* TX DMA Direction Error Interrupt */
IRQ_MAC_STMDONE  /* Station Mgt. Transfer Done Interrupt */

On BF537/6 the implementation is not straight forward since there are now
two chained chained_handlers.  A cleaner approach would have been to add
latter IRQs to the demux of IRQ_GENERIC_ERROR.
Signed-off-by: NMichael Hennerich <michael.hennerich@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

This makes room for off-chip IRQ controllers.
Signed-off-by: NMichael Hennerich <michael.hennerich@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NHarald Krapfenbauer <harald.krapfenbauer@bluetechnix.at>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The BF51x's Instruction SRAM is 32kB, not 48kB.
Signed-off-by: NMichael Hennerich <michael.hennerich@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

This lets people easily select the UART/SPORT consoles for early printk
while leveraging the pins declared in the boards file.
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Rather than keeping the pins in the actual driver and worrying about a
mess of Kconfig options, declare all the desired pin resources in the
boards file.  This lets people easily select the specific pins/ports for
the normal emulated UART as well as GPIOs for CTS/RTS.
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Rather than keeping the pins in the actual driver and worrying about a
mess of Kconfig options, declare all the desired pin resources in the
boards file.  This lets people easily select the specific pins/ports for
the normal UART as well as GPIOs for CTS/RTS.
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Whole lot of duplicated code here just went bye bye.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

While we're moving the BF54x code, have the BF54xM variants select the
normal BF54x values so that the rest of the Kconfig tree doesn't need to
check the BF54xM variant everytime it wants to check the BF54x.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Every Blackfin variant has the same DMA bit masks, so avoid duplicating
them over and over in each mach header.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

People should not be accessing OTP MMRs directly.  They should instead go
through the Blackfin ROM helper functions.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>