1. 09 2月, 2022 3 次提交
    • I
      dpaa2-eth: add support for software TSO · 3dc709e0
      Ioana Ciornei 提交于
      This patch adds support for driver level TSO in the enetc driver using
      the TSO API.
      
      There is not much to say about this specific implementation. We are
      using the usual tso_build_hdr(), tso_build_data() to create each data
      segment, we create an array of S/G FDs where the first S/G entry is
      referencing the header data and the remaining ones the data portion.
      
      For the S/G Table buffer we use the same cache of buffers used on the
      other non-GSO cases - dpaa2_eth_sgt_get() and dpaa2_eth_sgt_recycle().
      
      We cannot keep a DMA coherent buffer for all the TSO headers because the
      DPAA2 architecture does not work in a ring based fashion so we just
      allocate a buffer each time.
      
      Even with these limitations we get the following improvement in TCP
      termination on the LX2160A SoC, on a single A72 core running at 2.2GHz.
      
      before: 6.38Gbit/s
      after:  8.48Gbit/s
      Signed-off-by: NIoana Ciornei <ioana.ciornei@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      3dc709e0
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      dpaa2-eth: work with an array of FDs · a4ca448e
      Ioana Ciornei 提交于
      Up until now, the __dpaa2_eth_tx function used a single FD on the stack
      to construct the structure to be enqueued. Since we are now preparing
      the ground work to add support for TSO done in software at the driver
      level, the same function needs to work with an array of FDs and enqueue
      as many as the build_*_fd functions create.
      
      Make the necessary adjustments in order to do this. These include:
      keeping an array of FDs in a percpu structure, cleaning up the necessary
      FDs before populating it and then, retrying the enqueue process up till
      all the generated FDs were enqueued or until we reach the maximum number
      retries.
      
      This patch does not change the fact that only a single FD will result
      from a __dpaa2_eth_tx call but rather just creates the necessary changes
      for the next patch.
      Signed-off-by: NIoana Ciornei <ioana.ciornei@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      a4ca448e
    • I
      dpaa2-eth: use the S/G table cache also for the normal S/G path · a4218aef
      Ioana Ciornei 提交于
      Instead of allocating memory for an S/G table each time a nonlinear skb
      is processed, and then freeing it on the Tx confirmation path, use the
      S/G table cache in order to reuse the memory.
      
      For this to work we have to change the size of the cached buffers so
      that it can hold the maximum number of scatterlist entries.
      
      Other than that, each allocate/free call is replaced by a call to the
      dpaa2_eth_sgt_get/dpaa2_eth_sgt_recycle functions, introduced in the
      previous patch.
      Signed-off-by: NIoana Ciornei <ioana.ciornei@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      a4218aef
  2. 16 12月, 2021 1 次提交
  3. 15 10月, 2021 1 次提交
    • I
      net: dpaa2: add adaptive interrupt coalescing · fc398bec
      Ioana Ciornei 提交于
      Add support for adaptive interrupt coalescing to the dpaa2-eth driver.
      First of all, ETHTOOL_COALESCE_USE_ADAPTIVE_RX is defined as a supported
      coalesce parameter and the requested state is configured through the
      dpio APIs added in the previous patch.
      
      Besides the ethtool API interaction, we keep track of how many bytes and
      frames are dequeued per CDAN (Channel Data Availability Notification)
      and update the Net DIM instance through the dpaa2_io_update_net_dim()
      API.
      Signed-off-by: NIoana Ciornei <ioana.ciornei@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      fc398bec
  4. 27 9月, 2021 1 次提交
  5. 03 4月, 2021 3 次提交
  6. 07 2月, 2021 1 次提交
  7. 10 1月, 2021 1 次提交
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      dpaa2-mac: export MAC counters even when in TYPE_FIXED · d87e6063
      Ioana Ciornei 提交于
      If the network interface object is connected to a MAC of TYPE_FIXED, the
      link status management is handled exclusively by the firmware. This does
      not mean that the driver cannot access the MAC counters and export them
      in ethtool.
      
      For this to happen, we open the attached dpmac device and keep a pointer
      to it in priv->mac. Because of this, all the checks in the driver of the
      following form 'if (priv->mac)' have to be updated to actually check
      the dpmac attribute and not rely on the presence of a non-NULL value.
      Signed-off-by: NIoana Ciornei <ioana.ciornei@nxp.com>
      Signed-off-by: NJakub Kicinski <kuba@kernel.org>
      d87e6063
  8. 03 10月, 2020 2 次提交
  9. 19 9月, 2020 3 次提交
    • Y
      dpaa2-eth: support PTP Sync packet one-step timestamping · c5521189
      Yangbo Lu 提交于
      This patch is to add PTP sync packet one-step timestamping support.
      Before egress, one-step timestamping enablement needs,
      
      - Enabling timestamp and FAS (Frame Annotation Status) in
        dpni buffer layout.
      
      - Write timestamp to frame annotation and set PTP bit in
        FAS to mark as one-step timestamping event.
      
      - Enabling one-step timestamping by dpni_set_single_step_cfg()
        API, with offset provided to insert correction time on frame.
        The offset must respect all MAC headers, VLAN tags and other
        protocol headers accordingly. The correction field update can
        consider delays up to one second. So PTP frame needs to be
        filtered and parsed, and written timestamp into Sync frame
        originTimestamp field.
      
      The operation of API dpni_set_single_step_cfg() has to be done
      when no one-step timestamping frames are in flight. So we have
      to make sure the last one-step timestamping frame has already
      been transmitted on hardware before starting to send the current
      one. The resolution is,
      
      - Utilize skb->cb[0] to mark timestamping request per packet.
        If it is one-step timestamping PTP sync packet, queue to skb queue.
        If not, transmit immediately.
      
      - Schedule a work to transmit skbs in skb queue.
      
      - mutex lock is used to ensure the last one-step timestamping packet
        has already been transmitted on hardware through TX confirmation queue
        before transmitting current packet.
      Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      c5521189
    • Y
      dpaa2-eth: utilize skb->cb[0] for hardware timestamping · 1cf773bd
      Yangbo Lu 提交于
      This patch is a preparation for next hardware one-step timestamping
      support. For DPAA2, the one step timestamping configuration on
      hardware registers has to be done when there is no one-step timestamping
      packet in flight. So we will have to use workqueue and skb queue
      for such packets transmitting, to make sure waiting the last packet has
      already been sent on hardware, and starting to transmit the current one.
      
      So the tx timestamping flag in private data may not reflect the actual
      request for the one-step timestamping packets of skb queue. This also
      affects skb headroom allocation. Let's use skb->cb[0] to mark the
      timestamping request for each skb.
      Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      1cf773bd
    • Y
      dpaa2-eth: define a global ptp_qoriq structure pointer · d21c784c
      Yangbo Lu 提交于
      Define a global ptp_qoriq structure pointer, and export to use.
      The ptp clock operations will be used in dpaa2-eth driver.
      For example, supporting one step timestamping needs to write
      current time to hardware frame annotation before sending and
      then hardware inserts the delay time on frame during sending.
      So in driver, at least clock gettime operation will be needed
      to make sure right time is written to hardware frame annotation
      for one step timestamping.
      Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      d21c784c
  10. 22 7月, 2020 1 次提交
  11. 30 6月, 2020 2 次提交
  12. 02 6月, 2020 7 次提交
  13. 17 5月, 2020 1 次提交
  14. 16 5月, 2020 1 次提交
  15. 08 5月, 2020 1 次提交
  16. 26 4月, 2020 1 次提交
  17. 23 4月, 2020 3 次提交
  18. 01 11月, 2019 1 次提交
    • I
      dpaa2-eth: add MAC/PHY support through phylink · 71947923
      Ioana Ciornei 提交于
      The dpaa2-eth driver now has support for connecting to its associated
      PHY device found through standard OF bindings.
      
      This happens when the DPNI object (that the driver probes on) gets
      connected to a DPMAC. When that happens, the device tree is looked up by
      the DPMAC ID, and the associated PHY bindings are found.
      
      The old logic of handling the net device's link state by hand still
      needs to be kept, as the DPNI can be connected to other devices on the
      bus than a DPMAC: other DPNI, DPSW ports, etc. This logic is only
      engaged when there is no DPMAC (and therefore no phylink instance)
      attached.
      
      The MC firmware support multiple type of DPMAC links: TYPE_FIXED,
      TYPE_PHY. The TYPE_FIXED mode does not require any DPMAC management from
      Linux side, and as such, the driver will not handle such a DPMAC.
      
      Although PHYLINK typically handles SFP cages and in-band AN modes, for
      the moment the driver only supports the RGMII interfaces found on the
      LX2160A. Support for other modes will come later.
      Signed-off-by: NIoana Ciornei <ioana.ciornei@nxp.com>
      Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      71947923
  19. 07 10月, 2019 1 次提交
  20. 30 8月, 2019 1 次提交
    • I
      dpaa2-eth: Add pause frame support · 8eb3cef8
      Ioana Radulescu 提交于
      Starting with firmware version MC10.18.0, we have support for
      L2 flow control. Asymmetrical configuration (Rx or Tx only) is
      supported, but not pause frame autonegotioation.
      
      Pause frame configuration is done via ethtool. By default, we start
      with flow control enabled on both Rx and Tx. Changes are propagated
      to hardware through firmware commands, using two flags (PAUSE,
      ASYM_PAUSE) to specify Rx and Tx pause configuration, as follows:
      
      PAUSE | ASYM_PAUSE | Rx pause | Tx pause
      ----------------------------------------
        0   |     0      | disabled | disabled
        0   |     1      | disabled | enabled
        1   |     0      | enabled  | enabled
        1   |     1      | enabled  | disabled
      
      The hardware can automatically send pause frames when the number
      of buffers in the pool goes below a predefined threshold. Due to
      this, flow control is incompatible with Rx frame queue taildrop
      (both mechanisms target the case when processing of ingress
      frames can't keep up with the Rx rate; for large frames, the number
      of buffers in the pool may never get low enough to trigger pause
      frames as long as taildrop is enabled). So we set pause frame
      generation and Rx FQ taildrop as mutually exclusive.
      Signed-off-by: NIoana Radulescu <ruxandra.radulescu@nxp.com>
      Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      8eb3cef8
  21. 13 6月, 2019 2 次提交
  22. 27 5月, 2019 1 次提交
  23. 17 4月, 2019 1 次提交
    • I
      dpaa2-eth: Add flow steering support without masking · 2d680237
      Ioana Ciocoi Radulescu 提交于
      On platforms that lack a TCAM (like LS1088A), masking of
      flow steering keys is not supported. Until now we didn't
      offer flow steering capabilities at all on these platforms,
      since our driver implementation configured a "comprehensive"
      FS key (containing all supported header fields), with masks
      used to ignore the fields not present in the rules provided
      by the user.
      
      We now allow ethtool rules that share a common key (i.e. have
      the same header fields). The FS key is now kept in the driver
      private data and initialized when the first rule is added to
      an empty table, rather than at probe time. If a rule with a new
      composition key is wanted, the user must first manually delete
      all previous rules.
      
      When building a FS table entry to pass to firmware, we still use
      the old building algorithm, which assumes an all-supported-fields
      key, and later collapse the fields which aren't actually needed.
      
      Masked rules are not supported; if provided, the mask value
      will be ignored. For firmware versions older than MC10.7.0
      (that only offer the legacy ABIs for configuring distribution
      keys) flow steering without masking support remains unavailable.
      Signed-off-by: NIoana Radulescu <ruxandra.radulescu@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      2d680237