- 24 2月, 2019 1 次提交
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由 Florian Fainelli 提交于
We are not specifying an explicit format argument but instead passing a string litteral which causes these two warnings to show up: drivers/net/dsa/mv88e6xxx/chip.c: In function 'mv88e6xxx_irq_poll_setup': drivers/net/dsa/mv88e6xxx/chip.c:483:2: warning: format not a string literal and no format arguments [-Wformat-security] chip->kworker = kthread_create_worker(0, dev_name(chip->dev)); ^~~~ drivers/net/dsa/mv88e6xxx/ptp.c: In function 'mv88e6xxx_ptp_setup': drivers/net/dsa/mv88e6xxx/ptp.c:403:4: warning: format not a string literal and no format arguments [-Wformat-security] dev_name(chip->dev)); ^~~~~~~~ LD [M] drivers/net/dsa/mv88e6xxx/mv88e6xxx.o Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com> Reviewed-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 22 2月, 2019 1 次提交
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由 Russell King 提交于
Add support for the bridge flags to Marvell 88e6xxx bridges, allowing the multicast and unicast flood properties to be controlled. These can be controlled on a per-port basis via commands such as: bridge link set dev lan1 flood on|off bridge link set dev lan1 mcast_flood on|off Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com> Reviewed-by: NVivien Didelot <vivien.didelot@gmail.com> Signed-off-by: NRussell King <rmk+kernel@armlinux.org.uk> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 14 2月, 2019 1 次提交
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由 John David Anglin 提交于
The GPIO interrupt controller on the espressobin board only supports edge interrupts. If one enables the use of hardware interrupts in the device tree for the 88E6341, it is possible to miss an edge. When this happens, the INTn pin on the Marvell switch is stuck low and no further interrupts occur. I found after adding debug statements to mv88e6xxx_g1_irq_thread_work() that there is a race in handling device interrupts (e.g. PHY link interrupts). Some interrupts are directly cleared by reading the Global 1 status register. However, the device interrupt flag, for example, is not cleared until all the unmasked SERDES and PHY ports are serviced. This is done by reading the relevant SERDES and PHY status register. The code only services interrupts whose status bit is set at the time of reading its status register. If an interrupt event occurs after its status is read and before all interrupts are serviced, then this event will not be serviced and the INTn output pin will remain low. This is not a problem with polling or level interrupts since the handler will be called again to process the event. However, it's a big problem when using level interrupts. The fix presented here is to add a loop around the code servicing switch interrupts. If any pending interrupts remain after the current set has been handled, we loop and process the new set. If there are no pending interrupts after servicing, we are sure that INTn has gone high and we will get an edge when a new event occurs. Tested on espressobin board. Fixes: dc30c35b ("net: dsa: mv88e6xxx: Implement interrupt support.") Signed-off-by: NJohn David Anglin <dave.anglin@bell.net> Tested-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 10 2月, 2019 1 次提交
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由 Andrew Lunn 提交于
By using an external PHY, ports 9 and 10 can support 2500BaseT. So set this link mode in the mask when validating. Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NHeiner Kallweit <hkallweit1@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 07 2月, 2019 1 次提交
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由 Miquel Raynal 提交于
On one hand, the mv88e6xxx driver has a work queue called in loop which will attempt register accesses after MDIO bus suspension, that entirely freezes the platform during suspend. On the other hand, the DSA core is not ready yet to support suspend to RAM operation because so far there is no way to recover reliably the switch configuration. To avoid the kernel to freeze when suspending with a switch driven by the mv88e6xxx driver, we choose to prevent the driver suspension and in the same way, the whole platform. Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: NAndrew Lunn <andrew@lunn.ch> Reviewed-by: NVivien Didelot <vivien.didelot@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 06 2月, 2019 1 次提交
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由 Andrew Lunn 提交于
The ATU port vector contains a bit per port of the switch. The code wrongly used it as a port number, and incremented a port counter. This resulted in the wrong interfaces counter being incremented, and potentially going off the end of the array of ports. Fix this by using the source port ID for the violation, which really is a port number. Reported-by: NChris Healy <Chris.Healy@zii.aero> Tested-by: NChris Healy <Chris.Healy@zii.aero> Fixes: 65f60e45 ("net: dsa: mv88e6xxx: Keep ATU/VTU violation statistics") Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 28 1月, 2019 1 次提交
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由 Andrew Lunn 提交于
Duec to a typo, mv88e6390_serdes_irq_setup() calls itself, rather than mv88e6390x_serdes_irq_setup(). It then blows the stack, and shortly after the machine blows up. Fixes: 2defda1f ("net: dsa: mv88e6xxx: Add support for SERDES on ports 2-8 for 6390X") Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 11 1月, 2019 1 次提交
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由 Andrew Lunn 提交于
The 6390 copper ports have an errata which require poking magic values into undocumented magic registers and then performing a software reset. Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 20 12月, 2018 1 次提交
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由 Andrew Lunn 提交于
The 6320 family of switches uses the same watchdog registers as the 6390. Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Reviewed-by: NVivien Didelot <vivien.didelot@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 18 12月, 2018 1 次提交
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由 Vivien Didelot 提交于
Currently the ethtool_regs version is set to 0 for all DSA drivers. Use this field to store the chip ID to simplify the pretty dump of any interfaces registered by the "dsa" driver. Signed-off-by: NVivien Didelot <vivien.didelot@gmail.com> Reviewed-by: NAndrew Lunn <andrew@lunn.ch> Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 16 11月, 2018 1 次提交
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由 Andrew Lunn 提交于
We already have a workaround for a couple of switches whose internal PHYs only have the Marvel OUI, but no model number. We detect such PHYs and give them the 6390 ID as the model number. However the mv88e6161 has two SERDES interfaces in the same address range as its internal PHYs. These suffer from the same problem, the Marvell OUI, but no model number. As a result, these SERDES interfaces were getting the same PHY ID as the mv88e6390, even though they are not PHYs, and the Marvell PHY driver was trying to drive them. Add a special case to stop this from happen. Reported-by: NChris Healy <Chris.Healy@zii.aero> Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 12 11月, 2018 5 次提交
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由 Andrew Lunn 提交于
The mv88e6161 would sometime fail to probe with a timeout waiting for the switch to complete an operation. This operation is supposed to clear the statistics counters. However, due to a read/modify/write, without the needed mask, the operation actually carried out was more random, with invalid parameters, resulting in the switch not responding. We need to preserve the histogram mode bits, so apply a mask to keep them. Reported-by: NChris Healy <Chris.Healy@zii.aero> Fixes: 40cff8fc ("net: dsa: mv88e6xxx: Fix stats histogram mode") Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Andrew Lunn 提交于
The 6390X family has 8 SERDES interfaces. When ports 9 and 10 are not using all their SERDES interfaces, the unused ones can be assigned to ports 2-8. Add support for interrupts from SERDES interfaces connected to these lower ports. Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Andrew Lunn 提交于
The 6390X family has 8 SERDES interfaces. This allows ports 9 and 10 to support up to 10Gbps using 4 SERDES interfaces. However, when lower speeds are used, which need fewer SERDES interfaces, the unused SERDES interfaces can be used by ports 2-8. The hardware defaults to ports 9 and 10 having all 4 SERDES interfaces assigned to them. This only gets changed when the interface is configured after what the SFP supports has been determined, or the 10G PHY completes auto-neg. For hardware designs which limit ports 9 and 10 to one or two SERDES interfaces, and place SFPs on the lower interfaces, this is too late. Those ports with SFP should not wait until ports 9/10 are up in order to get access to the SERDES interface. So change the default configuration when the driver is initialised. Configure ports 9 and 10 to 1000BaseX, so they use a single SERDES interface, freeing up the others. They can steal them back if they need them. Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Andrew Lunn 提交于
The X family variants support additional ports modes, for 10G operation, which the non-X variants don't have. Add a port_set_cmode() for non-X variants to enforce this. Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Andrew Lunn 提交于
Move .port_set_cmode next to .port_get_cmode. Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 18 10月, 2018 1 次提交
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由 Marek Behún 提交于
This is a fix for the port_set_speed method for the Topaz family. Currently the same method is used as for the Peridot family, but this is wrong for the SERDES port. On Topaz, the SERDES port is port 5, not 9 and 10 as in Peridot. Moreover setting alt_bit on Topaz only makes sense for port 0 (for (differentiating 100mbps vs 200mbps). The SERDES port does not support more than 2500mbps, so alt_bit does not make any difference. Signed-off-by: NMarek Behún <marek.behun@nic.cz> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 17 9月, 2018 1 次提交
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由 Andrew Lunn 提交于
Fix a cut/paste error and a typo which results in ATU miss violations not being reported. Fixes: 0977644c ("net: dsa: mv88e6xxx: Decode ATU problem interrupt") Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 13 9月, 2018 1 次提交
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由 Marek Vasut 提交于
The MV88E6xxx can have external PHYs attached to certain ports and those PHYs could even be on different MDIO bus than the one within the switch. This patch makes sure that ports with such PHYs are configured correctly according to the information provided by the PHY. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Andrew Lunn <andrew@lunn.ch> Reviewed-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 03 9月, 2018 2 次提交
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由 Andrew Lunn 提交于
The 6352 family has one SERDES interface, which can be used by either port 4 or port 5. Add interrupt support for the SERDES interface, and report when the link status changes. Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Andrew Lunn 提交于
After changing to the needed page, actually write the value to the register! Fixes: 09cb7dfd ("net: dsa: mv88e6xxx: describe PHY page and SerDes") Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 01 9月, 2018 1 次提交
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由 Marek Behún 提交于
On some boards the interrupt can be shared between multiple devices. For example on Turris Mox the interrupt is shared between all switches. Signed-off-by: NMarek Behun <marek.behun@nic.cz> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 15 8月, 2018 2 次提交
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由 Dan Carpenter 提交于
We added a new error path, but we need to drop the lock before we return. Fixes: 2d2e1dd2 ("net: dsa: mv88e6xxx: Cache the port cmode") Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com> Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Dan Carpenter 提交于
We are trying to test if these flags are set but there are some && vs & typos. Fixes: efd1ba6a ("net: dsa: mv88e6xxx: Add SERDES phydev_mac_change up for 6390") Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com> Reviewed-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 10 8月, 2018 12 次提交
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由 Andrew Lunn 提交于
When a port changes CMODE, the SERDES interface being used can change. Disable interrupts for the old SERDES interface, and enable interrupts on the new. Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Andrew Lunn 提交于
phylink wants to know when the MAC layers notices a change in the link. For the 6390 family, this is a change in the SERDES state. Add interrupt support for the SERDES interface used to implement SGMII/1000Base-X/2500Base-X. This is currently limited to ports 9 and 10. Support for the 10G SERDES and other ports will be added later, building on this basic framework. Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Andrew Lunn 提交于
An up coming change will register interrupts for individual switch ports, using the mv88e6xxx_port as the interrupt context information. Add members to the mv88e6xxx_port structure so we can link it back to the mv88e6xxx_chip member the port belongs to and the port number of the port. Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Andrew Lunn 提交于
The 6390 family has a number of SERDES interfaces per port. When the cmode changes, eg 1000Base-X to XAUI, the SERDES interface in use will also change. Power down the old SERDES interface and power up the new SERDES interface. Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Andrew Lunn 提交于
The ports CMODE indicates the type of link between the MAC and the PHY. It is used often in the SERDES code. Rather than read it each time, cache its value. Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Andrew Lunn 提交于
The 6390 has three different SERDES interface types. 2500Base-X is implemented by the SGMII/1000Base-X SERDES. So power on/off the correct SERDES. Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Andrew Lunn 提交于
Add a helper for accessing SERDES registers of the 6390 family. Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Andrew Lunn 提交于
There is a need to add more functions manipulating the SERDES interfaces. Cleanup the namespace. Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Andrew Lunn 提交于
The 6390 has two SERDES interfaces, used by ports 9 and 10. The 6390X has eight SERDES interfaces. These allow ports 9 and 10 to do 10G. Or if lower speeds are used, some of the SERDES interfaces can be used by ports 2-8 for 1000Base-X. Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Andrew Lunn 提交于
The 6390 family has 8 SERDES lanes. What ports use these lanes depends on how ports 9 and 10 are configured. If 9 and 10 does not make use of a line, one of the lower ports can use it. Add a function to return the lane a port is using, if any, and simplify the code to power up/down the lane. Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Russell King 提交于
Add rudimentary phylink support to mv88e6xxx. TODO: - needs to call phylink_mac_change() when the port link comes up/goes down. Signed-off-by: NRussell King <rmk+kernel@armlinux.org.uk> Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Andrew Lunn 提交于
The 6185 can enable/disable 802.3z pause be setting the MyPause bit in the port status register. Add an op to support this. Signed-off-by: NRussell King <rmk+kernel@armlinux.org.uk> Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 01 8月, 2018 1 次提交
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由 Andrew Lunn 提交于
Version 1 of the patch adding SERDES support to the 88E6141/6341 correctly added the ops to the 88E6141/6341. However, by the time version 3 was committed, the ops had moved to the 88E6085/6175. Put them back where they belong. Fixes: 5bafeb6e ("net: dsa: mv88e6xxx: 88E6141/6341 SERDES support") Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 22 7月, 2018 1 次提交
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由 Uwe Kleine-König 提交于
free_irq() waits until all handlers for this IRQ have completed. As the relevant handler (mv88e6xxx_g1_irq_thread_fn()) takes the chip's reg_lock it might never return if the thread calling free_irq() holds this lock. For the same reason kthread_cancel_delayed_work_sync() in the polling case must not hold this lock. Also first free the irq (or stop the worker respectively) such that mv88e6xxx_g1_irq_thread_work() isn't called any more before the irq mappings are dropped in mv88e6xxx_g1_irq_free_common() to prevent the worker thread to call handle_nested_irq(0) which results in a NULL-pointer exception. Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 19 7月, 2018 2 次提交
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由 Andrew Lunn 提交于
For slow processors using bit-banging MDIO, 20ms can be too short a timeout when waiting for the transmit timestamp to become available. Double it to 40ms. Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Acked-by: NRichard Cochran <richardcochran@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Andrew Lunn 提交于
For the 6352 and newer switches, the PTP Ethertype defaults to ETH_P_1588. Hence it was not explicitly set. The 6165 however defaults to 0. So explicitly set the EtherType. Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Acked-by: NRichard Cochran <richardcochran@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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