- 09 10月, 2010 11 次提交
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由 Stepan Moskovchenko 提交于
Add the platform data for the IOMMUs found on the Qualcomm msm8x60 SoC. Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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由 Stepan Moskovchenko 提交于
Add support for the IOMMUs found on the upcoming Qualcomm MSM8x60 chips. These IOMMUs allow virtualization of the address space used by most of the multimedia cores on these chips. Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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由 Jeff Ohlstein 提交于
The MSM8x60 has a different physical memory offset than other targets. Signed-off-by: NJeff Ohlstein <johlstei@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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由 Daniel Walker 提交于
Some MSM targets don't select the debug UART in this way. For those we need to disable this selection mechanism. Signed-off-by: NDaniel Walker <dwalker@codeaurora.org> Signed-off-by: NJeff Ohlstein <johlstei@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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由 Daniel Walker 提交于
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org> Signed-off-by: NJeff Ohlstein <johlstei@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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由 Steve Muckle 提交于
The existing MSM irq entry macro is specific to a VIC implementation. Renaming this makes room for irq support based on other interrupt controllers. Signed-off-by: NSteve Muckle <smuckle@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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由 Steve Muckle 提交于
Board configuration for MSM8X60 emulation on RUMI3. Signed-off-by: NSteve Muckle <smuckle@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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由 Jeff Ohlstein 提交于
Signed-off-by: NJeff Ohlstein <johlstei@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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由 Abhijeet Dharmapurikar 提交于
Define the interrupt map in irq-8x60.h Signed-off-by: NAbhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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由 Steve Muckle 提交于
IRQ assignments are different for MSM8X60 than other existing MSMs. Signed-off-by: NSteve Muckle <smuckle@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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由 Steve Muckle 提交于
MSM8X60 has different IO mappings than previous MSMs. Signed-off-by: NSteve Muckle <smuckle@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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- 07 10月, 2010 2 次提交
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由 Gregory Bean 提交于
Now that all supported gpio_tlmm_config-using boards are using gpiomux, remove the deprecated code. Signed-off-by: NGregory Bean <gbean@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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由 Gregory Bean 提交于
Add the 'gpiomux' api, which addresses the following shortcomings of existing tlmm api: - gpio power-collapse, which is managed by a peripheral processor on other targets, must be managed by the application processor on the 8x60. - The enable/disable flag of the legacy gpio_tlmm_config api is not applicable on the 8x60, and causes confusion. - The gpio 'direction' bits are meaningless for all func_sel configurations except for generic-gpio mode (func_sel 0), in which case the gpio_direction_* functions should be used. Having these bits in the tlmm api leads to confusion and misuse of the gpiolib api, and they have been removed in gpiomux. - The functional api of the legacy system ran contrary to the typical use-case, which is a single massive configuration at boot. Rather than forcing hundreds of 'config' function calls, the new api allows data to be configured with a single table. gpiomux_get and gpiomux_put are meant to be called automatically when gpio_request and gpio_free are called, giving automatic gpiomux/tlmm control to those drivers/lines with simple power profiles - in the simplest cases, an entry in the gpiomux table and the correct usage of gpiolib is all that is required to get proper gpio power control. Signed-off-by: NGregory Bean <gbean@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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- 02 10月, 2010 1 次提交
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由 Nicolas Pitre 提交于
VMALLOC_END is supposed to be an absolute value, while PAGE_OFFSET may vary depending on the selected user:kernel memory split mode through CONFIG_VMSPLIT_*. In fact, the goal of moving PAGE_OFFSET down is to accommodate more directly addressed RAM by the kernel below the vmalloc area, and having VMALLOC_END move along PAGE_OFFSET is rather against the very reason why PAGE_OFFSET can be moved in the first place. Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
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- 10 8月, 2010 2 次提交
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由 Sahitya Tummala 提交于
Rename mmc_platform_data to msm_mmc_platform_data as it is used only by MSM platform. Signed-off-by: NSahitya Tummala <stummala@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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由 Sahitya Tummala 提交于
Add msm_add_sdcc() prototype to mach/board.h to fix the checkpatch warning. Signed-off-by: NSahitya Tummala <stummala@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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- 16 6月, 2010 1 次提交
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由 Pavel Machek 提交于
Signed-off-by: NPavel Machek <pavel@ucw.cz> [dwalker@codeaurora.org: renamed to trout, checkpatch cleanup] Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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- 14 5月, 2010 14 次提交
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由 Daniel Walker 提交于
The MSM7x30 does not have a separate bank of memory for shared memory communication with the radio CPU. Set the kernel base address 2MB in, to use this first 2MB for this purpose. Signed-off-by: NDaniel Walker <dwalker@codeaurora.org> Signed-off-by: NDavid Brown <davidb@codeaurora.org> Signed-off-by: NGregory Bean <gbean@codeaurora.org> Signed-off-by: NAbhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
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由 Daniel Walker 提交于
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org> Signed-off-by: NDavid Brown <davidb@codeaurora.org> Signed-off-by: NGregory Bean <gbean@codeaurora.org> Signed-off-by: NAbhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
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由 Daniel Walker 提交于
The MSM SOC's DMA controller contains several security domains. On the MSM7x00, only security domain 3 is accessible to our CPU. The 7x30, however, uses security domain 2. Fix up the register definition macros to select this appropriately, based on configured target. Signed-off-by: NDaniel Walker <dwalker@codeaurora.org> Signed-off-by: NDavid Brown <davidb@codeaurora.org> Signed-off-by: NGregory Bean <gbean@codeaurora.org> Signed-off-by: NAbhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
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由 Daniel Walker 提交于
Add a header describing the io regions for MSM7x30. Signed-off-by: NDaniel Walker <dwalker@codeaurora.org> Signed-off-by: NDavid Brown <davidb@codeaurora.org> Signed-off-by: NGregory Bean <gbean@codeaurora.org> Signed-off-by: NAbhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
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由 Daniel Walker 提交于
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org> Signed-off-by: NDavid Brown <davidb@codeaurora.org> Signed-off-by: NGregory Bean <gbean@codeaurora.org> Signed-off-by: NAbhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
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由 Daniel Walker 提交于
Support different RAM base addresses used by Qualcomm SOCs, with QSD8x50 as the first addtional one. Signed-off-by: NDaniel Walker <dwalker@codeaurora.org> Signed-off-by: NDavid Brown <davidb@codeaurora.org> Signed-off-by: NGregory Bean <gbean@codeaurora.org> Signed-off-by: NAbhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
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由 Daniel Walker 提交于
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org> Signed-off-by: NDavid Brown <davidb@codeaurora.org> Signed-off-by: NGregory Bean <gbean@codeaurora.org> Signed-off-by: NAbhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
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由 Daniel Walker 提交于
Add a header describing the io regions for QSD8x50. Signed-off-by: NDaniel Walker <dwalker@codeaurora.org> Signed-off-by: NDavid Brown <davidb@codeaurora.org> Signed-off-by: NGregory Bean <gbean@codeaurora.org> Signed-off-by: NAbhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
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由 Daniel Walker 提交于
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org> Signed-off-by: NDavid Brown <davidb@codeaurora.org> Signed-off-by: NGregory Bean <gbean@codeaurora.org> Signed-off-by: NAbhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
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由 Gregory Bean 提交于
GPIO support for Qualcomm SOCs requires interaction with the radio (baseband processor). This API allows the different boards to enable GPIO through the radio processor in a generic way. Signed-off-by: NGregory Bean <gbean@codeaurora.org> Signed-off-by: NDavid Brown <davidb@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org> Signed-off-by: NAbhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
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由 Daniel Walker 提交于
The 'PCOM' method of clock control (commands issued to the radio CPU) is shared across several (but not all) Qualcomm SOCs. Generalize this clock mechanism so these other SOCs can be added. Signed-off-by: NGregory Bean <gbean@codeaurora.org> Signed-off-by: NDavid Brown <davidb@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org> Signed-off-by: NAbhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
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由 Gregory Bean 提交于
Scorpion-based SOCs from Qualcomm use a different interrupt controller 'sirc'. Signed-off-by: NGregory Bean <gbean@codeaurora.org> Signed-off-by: NDavid Brown <davidb@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org> Signed-off-by: NAbhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
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由 Gregory Bean 提交于
msm_iomap.h is specific to the MSM7x00 series devices. Generalize this in preparation to support more devices. Signed-off-by: NGregory Bean <gbean@codeaurora.org> Signed-off-by: NDavid Brown <davidb@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org> Signed-off-by: NAbhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
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由 Gregory Bean 提交于
irqs.h is specific to the MSM7x00 series devices. Generalize this in preparation to support more devices. Signed-off-by: NGregory Bean <gbean@codeaurora.org> Signed-off-by: NDavid Brown <davidb@codeaurora.org> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org> Signed-off-by: NAbhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
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- 13 5月, 2010 7 次提交
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由 Daniel Walker 提交于
Also drops the old mddi structure, which conflicts with the new file. Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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由 Daniel Walker 提交于
This cleans up coding style. There are no run time changes. Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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由 Dima Zavin 提交于
Signed-off-by: NDima Zavin <dima@android.com> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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由 Brian Swetland 提交于
Some smd clients may write from multiple threads, in which case it's not safe to call smd_write without holding a lock. smd_write_atomic() provides the same functionality as smd_write() but obtains the smd lock first. Signed-off-by: NBrian Swetland <swetland@google.com> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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由 Brian Swetland 提交于
This code provides the low level interface to the "shared memory state machine" (smsm), and the virtual serial channels (smd), used to communicate with the baseband processor. Higher level transports (rpc, ethernet, AT command channel, etc) ride on top of this. Signed-off-by: NBrian Swetland <swetland@google.com>
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由 Steve Muckle 提交于
Keep track of the success/failure of the last vreg proc comm command, and return that on debugfs reads. Signed-off-by: NSteve Muckle <smuckle@quicinc.com>
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由 Daniel Walker 提交于
This adds acpuclock-arm11.c from Google. This provides control over the cpu frequency for arm11 cpu's. This has shared authorship between Google, and Qualcomm. Most of it was written by Mike Chan at Google. Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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- 19 3月, 2010 1 次提交
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由 San Mehat 提交于
Based on a patch from Brent DeGraaf: "The datamover supports channels which can be shared amongst devices. As a result, the actual data transfer may occur some time after the request is queued up. Some devices such as mmc host controllers will timeout if a command is issued too far in advance of the actual transfer, so if dma to other devices on the same channel is already in progress or queued up, the added delay can cause pending transfers to fail before they start. This change extends the api to allow a user callback to be invoked just before the actual transfer takes place, thus allowing actions directly associated with the dma transfer, such as device commands, to be invoked with precise timing. Without this mechanism, there is no way for a driver to realize this timing. Also adds a user pointer to the command structure for use by the caller to reference information that may be needed by the callback routine for proper identification and processing associated with that specific request. This change is necessary to fix problems associated with excessive command timeouts and race conditions in the mmc driver." This patch also fixes all the callers of msm_dmov_enqueue_cmd() to ensure their callback function is NULL. Signed-off-by: NSan Mehat <san@google.com> Cc: Brent DeGraaf <bdegraaf@quicinc.com> Cc: Brian Swetland <swetland@google.com> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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- 13 2月, 2010 1 次提交
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由 Tony Lindgren 提交于
Otherwise more complicated uart configuration won't be possible. We can use r1 for tmp register for both head.S and debug.S. NOTE: This patch depends on another patch to add the the tmp register into all debug-macro.S files. That can be done with: $ sed -i -e "s/addruart,rx|addruart, rx/addruart, rx, tmp/" arch/arm/*/include/*/debug-macro.S Signed-off-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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