1. 07 7月, 2021 1 次提交
    • K
      arm64: errata: add option to disable cache readunique prefetch on HIP08 · 3b876a78
      Kai Shen 提交于
      hulk inclusion
      category: feature
      bugzilla: https://gitee.com/openeuler/kernel/issues/I3ZFV2
      CVE: NA
      
      -----------------------------------------------------------
      
      Random performance decreases appear on cases of Hackbench which test
      pipe or socket communication among multi-threads on Hisi HIP08 SoC.
      Cache sharing which caused by the change of the data layout and the
      cache readunique prefetch mechanism both lead to this problem.
      
      Readunique mechanism which may caused by store operation will invalid
      cachelines on other cores during data fetching stage which can cause
      cacheline invalidation happens frequently in a sharing data access
      situation.
      
      Disable cache readunique prefetch can trackle this problem.
      Test cases are like:
          for i in 20;do
              echo "--------pipe thread num=$i----------"
              for j in $(seq 1 10);do
                  ./hackbench -pipe $i thread 1000
              done
          done
      
      We disable readunique prefetch only in el2 for in el1 disabling
      readunique prefetch may cause panic due to lack of related priority
      which often be set in BIOS.
      
      Introduce CONFIG_HISILICON_ERRATUM_HIP08_RU_PREFETCH and disable RU
      prefetch using boot cmdline 'readunique_prefetch=off'.
      Signed-off-by: NKai Shen <shenkai8@huawei.com>
      Signed-off-by: NHanjun Guo <guohanjun@huawei.com>
      [XQ: adjusted context]
      Signed-off-by: NXie XiuQi <xiexiuqi@huawei.com>
      Reviewed-by: NHanjun Guo <guohanjun@huawei.com>
      Signed-off-by: NCheng Jian <cj.chengjian@huawei.com>
      Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
      3b876a78
  2. 06 7月, 2021 39 次提交