1. 11 12月, 2018 5 次提交
    • L
      iommu/vt-d: Reserve a domain id for FL and PT modes · 3b33d4ab
      Lu Baolu 提交于
      Vt-d spec rev3.0 (section 6.2.3.1) requires that each pasid
      entry for first-level or pass-through translation should be
      programmed with a domain id different from those used for
      second-level or nested translation. It is recommended that
      software could use a same domain id for all first-only and
      pass-through translations.
      
      This reserves a domain id for first-level and pass-through
      translations.
      
      Cc: Ashok Raj <ashok.raj@intel.com>
      Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
      Cc: Kevin Tian <kevin.tian@intel.com>
      Cc: Liu Yi L <yi.l.liu@intel.com>
      Cc: Sanjay Kumar <sanjay.k.kumar@intel.com>
      Signed-off-by: NLu Baolu <baolu.lu@linux.intel.com>
      Signed-off-by: NJoerg Roedel <jroedel@suse.de>
      3b33d4ab
    • L
      iommu/vt-d: Add 256-bit invalidation descriptor support · 5d308fc1
      Lu Baolu 提交于
      Intel vt-d spec rev3.0 requires software to use 256-bit
      descriptors in invalidation queue. As the spec reads in
      section 6.5.2:
      
      Remapping hardware supporting Scalable Mode Translations
      (ECAP_REG.SMTS=1) allow software to additionally program
      the width of the descriptors (128-bits or 256-bits) that
      will be written into the Queue. Software should setup the
      Invalidation Queue for 256-bit descriptors before progra-
      mming remapping hardware for scalable-mode translation as
      128-bit descriptors are treated as invalid descriptors
      (see Table 21 in Section 6.5.2.10) in scalable-mode.
      
      This patch adds 256-bit invalidation descriptor support
      if the hardware presents scalable mode capability.
      
      Cc: Ashok Raj <ashok.raj@intel.com>
      Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
      Cc: Kevin Tian <kevin.tian@intel.com>
      Signed-off-by: NSanjay Kumar <sanjay.k.kumar@intel.com>
      Signed-off-by: NLiu Yi L <yi.l.liu@intel.com>
      Signed-off-by: NLu Baolu <baolu.lu@linux.intel.com>
      Signed-off-by: NJoerg Roedel <jroedel@suse.de>
      5d308fc1
    • L
      iommu/vt-d: Move page table helpers into header · 4f2ed183
      Lu Baolu 提交于
      So that they could also be used in other source files.
      
      Cc: Ashok Raj <ashok.raj@intel.com>
      Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
      Cc: Kevin Tian <kevin.tian@intel.com>
      Cc: Liu Yi L <yi.l.liu@intel.com>
      Cc: Sanjay Kumar <sanjay.k.kumar@intel.com>
      Signed-off-by: NLu Baolu <baolu.lu@linux.intel.com>
      Reviewed-by: NAshok Raj <ashok.raj@intel.com>
      Reviewed-by: NKevin Tian <kevin.tian@intel.com>
      Signed-off-by: NJoerg Roedel <jroedel@suse.de>
      4f2ed183
    • L
      iommu/vt-d: Manage scalalble mode PASID tables · 0bbeb01a
      Lu Baolu 提交于
      In scalable mode, pasid structure is a two level table with
      a pasid directory table and a pasid table. Any pasid entry
      can be identified by a pasid value in below way.
      
         1
         9                       6 5      0
          .-----------------------.-------.
          |              PASID    |       |
          '-----------------------'-------'    .-------------.
                   |                    |      |             |
                   |                    |      |             |
                   |                    |      |             |
                   |     .-----------.  |      .-------------.
                   |     |           |  |----->| PASID Entry |
                   |     |           |  |      '-------------'
                   |     |           |  |Plus  |             |
                   |     .-----------.  |      |             |
                   |---->| DIR Entry |-------->|             |
                   |     '-----------'         '-------------'
      .---------.  |Plus |           |
      | Context |  |     |           |
      |  Entry  |------->|           |
      '---------'        '-----------'
      
      This changes the pasid table APIs to support scalable mode
      PASID directory and PASID table. It also adds a helper to
      get the PASID table entry according to the pasid value.
      
      Cc: Ashok Raj <ashok.raj@intel.com>
      Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
      Cc: Kevin Tian <kevin.tian@intel.com>
      Signed-off-by: NSanjay Kumar <sanjay.k.kumar@intel.com>
      Signed-off-by: NLiu Yi L <yi.l.liu@intel.com>
      Signed-off-by: NLu Baolu <baolu.lu@linux.intel.com>
      Reviewed-by: NAshok Raj <ashok.raj@intel.com>
      Signed-off-by: NJoerg Roedel <jroedel@suse.de>
      0bbeb01a
    • L
      iommu/vt-d: Enumerate the scalable mode capability · 765b6a98
      Lu Baolu 提交于
      The Intel vt-d spec rev3.0 introduces a new translation
      mode called scalable mode, which enables PASID-granular
      translations for first level, second level, nested and
      pass-through modes. At the same time, the previous
      Extended Context (ECS) mode is deprecated (no production
      ever implements ECS).
      
      This patch adds enumeration for Scalable Mode and removes
      the deprecated ECS enumeration. It provides a boot time
      option to disable scalable mode even hardware claims to
      support it.
      
      Cc: Ashok Raj <ashok.raj@intel.com>
      Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
      Cc: Kevin Tian <kevin.tian@intel.com>
      Signed-off-by: NSanjay Kumar <sanjay.k.kumar@intel.com>
      Signed-off-by: NLiu Yi L <yi.l.liu@intel.com>
      Signed-off-by: NLu Baolu <baolu.lu@linux.intel.com>
      Reviewed-by: NAshok Raj <ashok.raj@intel.com>
      Reviewed-by: NKevin Tian <kevin.tian@intel.com>
      Signed-off-by: NJoerg Roedel <jroedel@suse.de>
      765b6a98
  2. 23 11月, 2018 1 次提交
    • S
      iommu/vt-d: Handle domain agaw being less than iommu agaw · 3569dd07
      Sohil Mehta 提交于
      The Intel IOMMU driver opportunistically skips a few top level page
      tables from the domain paging directory while programming the IOMMU
      context entry. However there is an implicit assumption in the code that
      domain's adjusted guest address width (agaw) would always be greater
      than IOMMU's agaw.
      
      The IOMMU capabilities in an upcoming platform cause the domain's agaw
      to be lower than IOMMU's agaw. The issue is seen when the IOMMU supports
      both 4-level and 5-level paging. The domain builds a 4-level page table
      based on agaw of 2. However the IOMMU's agaw is set as 3 (5-level). In
      this case the code incorrectly tries to skip page page table levels.
      This causes the IOMMU driver to avoid programming the context entry. The
      fix handles this case and programs the context entry accordingly.
      
      Fixes: de24e553 ("iommu/vt-d: Simplify domain_context_mapping_one")
      Cc: <stable@vger.kernel.org>
      Cc: Ashok Raj <ashok.raj@intel.com>
      Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
      Cc: Lu Baolu <baolu.lu@linux.intel.com>
      Reviewed-by: NLu Baolu <baolu.lu@linux.intel.com>
      Reported-by: NRamos Falcon, Ernesto R <ernesto.r.ramos.falcon@intel.com>
      Tested-by: NRicardo Neri <ricardo.neri-calderon@linux.intel.com>
      Signed-off-by: NSohil Mehta <sohil.mehta@intel.com>
      Signed-off-by: NJoerg Roedel <jroedel@suse.de>
      3569dd07
  3. 12 11月, 2018 2 次提交
  4. 10 11月, 2018 14 次提交
  5. 09 11月, 2018 15 次提交
  6. 08 11月, 2018 3 次提交