1. 25 5月, 2019 1 次提交
  2. 09 11月, 2018 1 次提交
    • T
      net: stmmac: Fix RX packet size > 8191 · 8137b6ef
      Thor Thayer 提交于
      Ping problems with packets > 8191 as shown:
      
      PING 192.168.1.99 (192.168.1.99) 8150(8178) bytes of data.
      8158 bytes from 192.168.1.99: icmp_seq=1 ttl=64 time=0.669 ms
      wrong data byte 8144 should be 0xd0 but was 0x0
      16    10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f
            20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f
      %< ---------------snip--------------------------------------
      8112  b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 ba bb bc bd be bf
            c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 ca cb cc cd ce cf
      8144  0 0 0 0 d0 d1
            ^^^^^^^
      Notice the 4 bytes of 0 before the expected byte of d0.
      
      Databook notes that the RX buffer must be a multiple of 4/8/16
      bytes [1].
      
      Update the DMA Buffer size define to 8188 instead of 8192. Remove
      the -1 from the RX buffer size allocations and use the new
      DMA Buffer size directly.
      
      [1] Synopsys DesignWare Cores Ethernet MAC Universal v3.70a
          [section 8.4.2 - Table 8-24]
      
      Tested on SoCFPGA Stratix10 with ping sweep from 100 to 8300 byte packets.
      
      Fixes: 286a8372 ("stmmac: add CHAINED descriptor mode support (V4)")
      Suggested-by: NJose Abreu <jose.abreu@synopsys.com>
      Signed-off-by: NThor Thayer <thor.thayer@linux.intel.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      8137b6ef
  3. 19 9月, 2018 1 次提交
    • J
      net: stmmac: Rework coalesce timer and fix multi-queue races · 8fce3331
      Jose Abreu 提交于
      This follows David Miller advice and tries to fix coalesce timer in
      multi-queue scenarios.
      
      We are now using per-queue coalesce values and per-queue TX timer.
      
      Coalesce timer default values was changed to 1ms and the coalesce frames
      to 25.
      
      Tested in B2B setup between XGMAC2 and GMAC5.
      Signed-off-by: NJose Abreu <joabreu@synopsys.com>
      Fixes: 	ce736788 ("net: stmmac: adding multiple buffers for TX")
      Cc: Florian Fainelli <f.fainelli@gmail.com>
      Cc: Neil Armstrong <narmstrong@baylibre.com>
      Cc: Jerome Brunet <jbrunet@baylibre.com>
      Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
      Cc: David S. Miller <davem@davemloft.net>
      Cc: Joao Pinto <jpinto@synopsys.com>
      Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
      Cc: Alexandre Torgue <alexandre.torgue@st.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      8fce3331
  4. 10 8月, 2018 2 次提交
  5. 04 6月, 2018 1 次提交
    • J
      net: stmmac: Add Flexible PPS support · 9a8a02c9
      Jose Abreu 提交于
      This adds support for Flexible PPS output (which is equivalent
      to per_out output of PTP subsystem).
      
      Tested using an oscilloscope and the following commands:
      
      1) Start PTP4L:
      	# ptp4l -A -4 -H -m -i eth0 &
      2) Set Flexible PPS frequency:
      	# echo <idx> <ts> <tns> <ps> <pns> > /sys/class/ptp/ptpX/period
      
      Where, ts/tns is start time and ps/pns is period time, and ptpX is ptp
      of eth0.
      Signed-off-by: NJose Abreu <joabreu@synopsys.com>
      Cc: David S. Miller <davem@davemloft.net>
      Cc: Joao Pinto <jpinto@synopsys.com>
      Cc: Vitor Soares <soares@synopsys.com>
      Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
      Cc: Alexandre Torgue <alexandre.torgue@st.com>
      Cc: Richard Cochran <richardcochran@gmail.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      9a8a02c9
  6. 11 5月, 2018 1 次提交
    • J
      net: stmmac: Add support for U32 TC filter using Flexible RX Parser · 4dbbe8dd
      Jose Abreu 提交于
      This adds support for U32 filter by using an HW only feature called
      Flexible RX Parser. This allow us to match any given packet field with a
      pattern and accept/reject or even route the packet to a specific DMA
      channel.
      
      Right now we only support acception or rejection of frame and we only
      support simple rules. Though, the Parser has the flexibility of jumping to
      specific rules as an if condition so complex rules can be established.
      
      This is only supported in GMAC5.10+.
      
      The following commands can be used to test this code:
      
      	1) Setup an ingress qdisk:
      	# tc qdisc add dev eth0 handle ffff: ingress
      
      	2) Setup a filter (e.g. filter by IP):
      	# tc filter add dev eth0 parent ffff: protocol ip u32 match ip \
      		src 192.168.0.3 skip_sw action drop
      
      In every tests performed we always used the "skip_sw" flag to make sure
      only the RX Parser was involved.
      Signed-off-by: NJose Abreu <joabreu@synopsys.com>
      Cc: David S. Miller <davem@davemloft.net>
      Cc: Joao Pinto <jpinto@synopsys.com>
      Cc: Vitor Soares <soares@synopsys.com>
      Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
      Cc: Alexandre Torgue <alexandre.torgue@st.com>
      Cc: Jakub Kicinski <kubakici@wp.pl>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      4dbbe8dd
  7. 24 4月, 2018 1 次提交
    • J
      net: stmmac: Implement logic to automatically select HW Interface · 5f0456b4
      Jose Abreu 提交于
      Move all the core version detection to a common place ("hwif.c") and
      implement a table which can be used to lookup the correct callbacks for
      each IP version.
      
      This simplifies the initialization flow of each IP version and eases
      future implementation of new IP versions.
      Signed-off-by: NJose Abreu <joabreu@synopsys.com>
      Cc: David S. Miller <davem@davemloft.net>
      Cc: Joao Pinto <jpinto@synopsys.com>
      Cc: Vitor Soares <soares@synopsys.com>
      Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
      Cc: Alexandre Torgue <alexandre.torgue@st.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      5f0456b4
  8. 17 4月, 2018 5 次提交
  9. 31 3月, 2018 1 次提交
    • J
      net: stmmac: Add support for DWMAC5 and implement Safety Features · 8bf993a5
      Jose Abreu 提交于
      This adds initial suport for DWMAC5 and implements the Automotive Safety
      Package which is available from core version 5.10.
      
      The Automotive Safety Pacakge (also called Safety Features) offers us
      with error protection in the core by implementing ECC Protection in
      memories, on-chip data path parity protection, FSM parity and timeout
      protection and Application/CSR interface timeout protection.
      
      In case of an uncorrectable error we call stmmac_global_err() and
      reconfigure the whole core.
      Signed-off-by: NJose Abreu <joabreu@synopsys.com>
      Cc: David S. Miller <davem@davemloft.net>
      Cc: Joao Pinto <jpinto@synopsys.com>
      Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
      Cc: Alexandre Torgue <alexandre.torgue@st.com>
      Cc: Andrew Lunn <andrew@lunn.ch>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      8bf993a5
  10. 23 1月, 2018 1 次提交
    • F
      net: stmmac: Fix reception of Broadcom switches tags · 8cad443e
      Florian Fainelli 提交于
      Broadcom tags inserted by Broadcom switches put a 4 byte header after
      the MAC SA and before the EtherType, which may look like some sort of 0
      length LLC/SNAP packet (tcpdump and wireshark do think that way). With
      ACS enabled in stmmac the packets were truncated to 8 bytes on
      reception, whereas clearing this bit allowed normal reception to occur.
      
      In order to make that possible, we need to pass a net_device argument to
      the different core_init() functions and we are dependent on the Broadcom
      tagger padding packets correctly (which it now does). To be as little
      invasive as possible, this is only done for gmac1000 when the network
      device is DSA-enabled (netdev_uses_dsa() returns true).
      Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
      Acked-by: NGiuseppe Cavallaro <peppe.cavallaro@st.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      8cad443e
  11. 20 12月, 2017 1 次提交
  12. 15 10月, 2017 2 次提交
  13. 26 5月, 2017 1 次提交
    • L
      net-next: stmmac: rework the speed selection · ca84dfb9
      LABBE Corentin 提交于
      The current stmmac_adjust_link() part which handle speed have
      some if (has_platform) code and my dwmac-sun8i will add more of them.
      
      So we need to handle better speed selection.
      Moreover the struct link member speed and port are hard to guess their
      purpose. And their unique usage are to be combined for writing speed.
      
      So this patch replace speed/port by simpler
      speed10/speed100/speed1000/speed_mask variables.
      
      In dwmac4_core_init and dwmac1000_core_init, port/speed value was used
      directly without using the struct link. This patch convert also their
      usage to speedxxx.
      Signed-off-by: NCorentin Labbe <clabbe.montjoie@gmail.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      ca84dfb9
  14. 14 4月, 2017 1 次提交
    • N
      net: stmmac: set total length of the packet to be transmitted in TDES3 · fe6af0e1
      Niklas Cassel 提交于
      Field FL/TPL in register TDES3 is not correctly set on GMAC4.
      TX appears to be functional on GMAC 4.10a even if this field is not set,
      however, to avoid relying on undefined behavior, set the length in TDES3.
      
      The field has a different meaning depending on if the TSE bit in TDES3
      is set or not (TSO). However, regardless of the TSE bit, the field is
      not optional. The field is already set correctly when the TSE bit is set.
      
      Since there is no limit for the number of descriptors that can be
      used for a single packet, the field should be set to the sum of
      the buffers contained in:
      [<desc with First Descriptor bit set> ... <desc n> ...
      <desc with Last Descriptor bit set>], which should be equal to skb->len.
      Signed-off-by: NNiklas Cassel <niklas.cassel@axis.com>
      Acked-by: NGiuseppe Cavallaro <peppe.cavallaro@st.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      fe6af0e1
  15. 25 3月, 2017 1 次提交
  16. 22 3月, 2017 2 次提交
  17. 16 3月, 2017 7 次提交
  18. 13 3月, 2017 9 次提交
  19. 25 2月, 2017 1 次提交