1. 06 7月, 2015 1 次提交
  2. 03 7月, 2015 1 次提交
  3. 30 6月, 2015 3 次提交
  4. 27 6月, 2015 3 次提交
  5. 12 6月, 2015 2 次提交
  6. 03 6月, 2015 1 次提交
  7. 29 5月, 2015 11 次提交
  8. 22 5月, 2015 1 次提交
    • D
      drm/i915/skl: Deinit/init the display at suspend/resume · 5d96d8af
      Damien Lespiau 提交于
      We need to re-init the display hardware when going out of suspend. This
      includes:
      
        - Hooking the PCH to the reset logic
        - Restoring CDCDLK
        - Enabling the DDB power
      
      Among those, only the CDCDLK one is a bit tricky. There's some
      complexity in that:
      
        - DPLL0 (which is the source for CDCLK) has two VCOs, each with a set
          of supported frequencies. As eDP also uses DPLL0 for its link rate,
          once DPLL0 is on, we restrict the possible eDP link rates the chosen
          VCO.
        - CDCLK also limits the bandwidth available to push pixels.
      
      So, as a first step, this commit restore what the BIOS set, until I can
      do more testing.
      
      In case that's of interest for the reviewer, I've unit tested the
      function that derives the decimal frequency field:
      
        #include <stdio.h>
        #include <stdint.h>
        #include <assert.h>
      
        #define ARRAY_SIZE(x) (sizeof(x) / sizeof(*(x)))
      
        static const struct dpll_freq {
                unsigned int freq;
                unsigned int decimal;
        } freqs[] = {
                { .freq = 308570, .decimal = 0b01001100111},
                { .freq = 337500, .decimal = 0b01010100001},
                { .freq = 432000, .decimal = 0b01101011110},
                { .freq = 450000, .decimal = 0b01110000010},
                { .freq = 540000, .decimal = 0b10000110110},
                { .freq = 617140, .decimal = 0b10011010000},
                { .freq = 675000, .decimal = 0b10101000100},
        };
      
        static void intbits(unsigned int v)
        {
                int i;
      
                for(i = 10; i >= 0; i--)
                        putchar('0' + ((v >> i) & 1));
        }
      
        static unsigned int freq_decimal(unsigned int freq /* in kHz */)
        {
                return (freq - 1000) / 500;
        }
      
        static void test_freq(const struct dpll_freq *entry)
        {
                unsigned int decimal = freq_decimal(entry->freq);
      
                printf("freq: %d, expected: ", entry->freq);
                intbits(entry->decimal);
                printf(", got: ");
                intbits(decimal);
                putchar('\n');
      
                assert(decimal == entry->decimal);
        }
      
        int main(int argc, char **argv)
        {
                int i;
      
                for (i = 0; i < ARRAY_SIZE(freqs); i++)
                        test_freq(&freqs[i]);
      
                return 0;
        }
      
      v2:
        - Rebase on top of -nightly
        - Use (freq - 1000) / 500 for the decimal frequency (Ville)
        - Fix setting the enable bit of HSW_NDE_RSTWRN_OPT (Ville)
        - Rename skl_display_{resume,suspend} to skl_{init,uninit}_cdclk to
          be consistent with the BXT code (Ville)
        - Store boot CDCLK in ddi_pll_init (Ville)
        - Merge dev_priv's skl_boot_cdclk into cdclk_freq
        - Use LCPLL_PLL_LOCK instead of (1 << 30) (Ville)
        - Replace various '0' by SKL_DPLL0 to be a bit more explicit that
          we're programming DPLL0
        - Busy poll the PCU before doing the frequency change. It takes about
          3/4 cycles, each separated by 10us, to get the ACK from the CPU
          (Ville)
      
      v3:
        - Restore dev_priv->skl_boot_cdclk, leaving unification with
          dev_priv->cdclk_freq for a later patch (Daniel, Ville)
      Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      5d96d8af
  9. 20 5月, 2015 3 次提交
  10. 08 5月, 2015 4 次提交
  11. 30 4月, 2015 2 次提交
  12. 16 4月, 2015 8 次提交