1. 16 7月, 2019 1 次提交
  2. 12 7月, 2019 2 次提交
  3. 11 7月, 2019 1 次提交
  4. 05 7月, 2019 1 次提交
  5. 01 7月, 2019 3 次提交
  6. 17 6月, 2019 1 次提交
  7. 12 6月, 2019 1 次提交
  8. 07 6月, 2019 2 次提交
  9. 06 6月, 2019 1 次提交
  10. 23 5月, 2019 4 次提交
    • G
      drm/i915/dp: Support DP ports YUV 4:2:0 output to GEN11 · 47d0ccec
      Gwan-gyeong Mun 提交于
      Bspec describes that GEN10 only supports capability of YUV 4:2:0 output to
      HDMI port and GEN11 supports capability of YUV 4:2:0 output to both DP and
      HDMI ports.
      
      v2: Minor style fix.
      Signed-off-by: NGwan-gyeong Mun <gwan-gyeong.mun@intel.com>
      Reviewed-by: NMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
      Signed-off-by: NJani Nikula <jani.nikula@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20190521121721.32010-7-gwan-gyeong.mun@intel.com
      47d0ccec
    • G
      drm/i915/dp: Change a link bandwidth computation for DP · 16668f48
      Gwan-gyeong Mun 提交于
      Data M/N calculations were assumed a bpp as RGB format. But when we are
      using YCbCr 4:2:0 output format on DP, we should change bpp calculations
      as YCbCr 4:2:0 format. The pipe_bpp value was assumed RGB format,
      therefore, it was multiplied with 3. But YCbCr 4:2:0 requires a multiplier
      value to 1.5.
      Therefore we need to divide pipe_bpp to 2 while DP output uses YCbCr4:2:0
      format.
       - RGB format bpp = bpc x 3
       - YCbCr 4:2:0 format bpp = bpc x 1.5
      
      But Link M/N values are calculated and applied based on the Full Clock for
      YCbCr 4:2:0. And DP YCbCr 4:2:0 does not need to pixel clock double for
      a dotclock caluation. Only for HDMI YCbCr 4:2:0 needs to pixel clock double
      for a dot clock calculation.
      
      It only affects dp and edp port which use YCbCr 4:2:0 output format.
      And for now, it does not consider a use case of DSC + YCbCr 4:2:0.
      
      v2:
        Addressed review comments from Ville.
        Remove a changing of pipe_bpp on intel_ddi_set_pipe_settings().
        Because the pipe is running at the full bpp, keep pipe_bpp as RGB
        even though YCbCr 4:2:0 output format is used.
        Add a link bandwidth computation for YCbCr4:2:0 output format.
      
      v3:
        Addressed reivew comments from Ville.
        In order to make codes simple, it adds and uses intel_dp_output_bpp()
        function.
      
      v6:
        Link M/N values are calculated and applied based on the Full Clock for
        YCbCr420. The Bit per Pixel needs to be adjusted for YUV420 mode as it
        requires only half of the RGB case.
          - Link M/N values are calculated and applied based on the Full Clock
          - Data M/N values needs to be calculated considering the data is half
            due to subsampling
        Remove a doubling of pixel clock on a dot clock calculator for
        DP YCbCr 4:2:0.
        Rebase and remove a duplicate setting of vsc_sdp.DB17.
        Add a setting of dynamic range bit to  vsc_sdp.DB17.
        Change Content Type bit to "Graphics" from "Not defined".
        Change a dividing of pipe_bpp to muliplying to constant values on a
        switch-case statement.
      
      v7:
        Addressed review comments from Ville.
        Move a setting of dynamic range bit and a setting of bpc which is based
        on pipe_bpp to a "drm/i915/dp: Program VSC Header and DB for Pixel
        Encoding/Colorimetry Format" commit.
        Change Content Type bit to "Not defined" from "Graphics".
      
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: NGwan-gyeong Mun <gwan-gyeong.mun@intel.com>
      Reviewed-by: NMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
      Signed-off-by: NJani Nikula <jani.nikula@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20190521121721.32010-6-gwan-gyeong.mun@intel.com
      16668f48
    • G
      drm/i915/dp: Program VSC Header and DB for Pixel Encoding/Colorimetry Format · 3c053a96
      Gwan-gyeong Mun 提交于
      Function intel_pixel_encoding_setup_vsc handles vsc header and data block
      setup for pixel encoding / colorimetry format.
      
      Setup VSC header and data block in function intel_pixel_encoding_setup_vsc
      for pixel encoding / colorimetry format as per dp 1.4a spec,
      section 2.2.5.7.1, table 2-119: VSC SDP Header Bytes, section 2.2.5.7.5,
      table 2-120:VSC SDP Payload for DB16 through DB18.
      
      v2:
        Minor style fix. [Maarten]
        Refer to commit ids instead of patchwork. [Maarten]
      
      v6: Rebase
      
      v7:
        Rebase and addressed review comments from Ville.
        Use a structure initializer instead of memset().
        Fix non-standard comment format.
        Remove a referring to specific commit.
        Add a setting of dynamic range bit to  vsc_sdp.DB17.
        Add a setting of bpc which is based on pipe_bpp.
        Remove duplicated checking of connector's ycbcr_420_allowed from
        intel_pixel_encoding_setup_vsc(). It is already checked from
        intel_dp_ycbcr420_config().
        Remove comments for VSC_SDP_EXTENSION_FOR_COLORIMETRY_SUPPORTED. It is
        already implemented on intel_dp_get_colorimetry_status().
      
      v8:
        A missing of setting bpc to VSC setup is the pretty fatal case, it
        replaces DRM_DEBUG_KMS() to MISSING_CASE(). [Maarten]
      
      v9: Use a changed member name of struct dp_sdp. it renamed to db from DB.
      
      Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: NGwan-gyeong Mun <gwan-gyeong.mun@intel.com>
      Reviewed-by: NMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
      Signed-off-by: NJani Nikula <jani.nikula@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20190521121721.32010-4-gwan-gyeong.mun@intel.com
      3c053a96
    • G
      drm/i915/dp: Add a config function for YCBCR420 outputs · 8e9d645c
      Gwan-gyeong Mun 提交于
      This patch checks a support of YCBCR420 outputs on an encoder level.
      If the input mode is YCBCR420-only mode then it prepares DP as an YCBCR420
      output, else it continues with RGB output mode.
      It set output_format to INTEL_OUTPUT_FORMAT_YCBCR420 in order to using
      a pipe scaler as RGB to YCbCr 4:4:4.
      
      v2:
        Addressed review comments from Ville.
        Style fixed with few naming.
        %s/config/crtc_state/
        %s/intel_crtc/crtc/
        If lscon is active, it makes not to call intel_dp_ycbcr420_config()
        to avoid to clobber of lspcon_ycbcr420_config() routine.
        And it move the 420_only check into the intel_dp_ycbcr420_config().
      
      v3: Fix uninitialized return value and it is reported by Dan Carpenter.
      
      v4:
        Addressed review comments from Ville.
        In order to avoid the extra indentation, it inverts if-clause on
        intel_dp_ycbcr420_config().
        Remove the error print where no errors print are allowed.
      
      v6: Rebase
      
      v7:
        Move intel_dp_get_colorimetry_status() to intel_dp from intel_psr.
        intel_dp_get_colorimetry_status() checks
        VSC_SDP_EXTENSION_FOR_COLORIMETRY_SUPPORTED bit in the
        DPRX_FEATURE_ENUMERATION_LIST register.
        And intel_dp_ycbcr420_config() uses intel_dp_get_colorimetry_status().
      
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: NGwan-gyeong Mun <gwan-gyeong.mun@intel.com>
      Reviewed-by: NMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
      Signed-off-by: NJani Nikula <jani.nikula@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20190521121721.32010-2-gwan-gyeong.mun@intel.com
      8e9d645c
  11. 17 5月, 2019 1 次提交
  12. 14 5月, 2019 6 次提交
  13. 03 5月, 2019 3 次提交
  14. 30 4月, 2019 6 次提交
  15. 26 4月, 2019 2 次提交
  16. 16 4月, 2019 1 次提交
  17. 12 4月, 2019 3 次提交
  18. 11 4月, 2019 1 次提交