This patch adds support to the Cadence PCIe controller in endpoint mode.

Since pieces of source code are shared with the host driver (Root
Complex mode), we create a new directory under drivers/pci dedicated to
the Cadence PCIe controller. The common code is placed into
drivers/pci/cadence/pcie-cadence.c and used by both the host and
endpoint controller drivers.
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@free-electrons.com>
Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>

This patch adds support to the Cadence PCIe controller in host mode.
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@free-electrons.com>
Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>

This patchs moves generic source code from
drivers/pci/host/pci-host-common.c into drivers/pci/probe.c.

Indeed the extracted lines of code were duplicated by many host
controller drivers. Regrouping them into a generic function gives a
change to properly share this code without introducing a useless
dependency to PCI_HOST_COMMON, which selects PCI_ECAM when not needed by
most host controller drivers.
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@free-electrons.com>
Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>

Call pci_free_resource_list() from pci_host_common_probe() when probing
fails, as done inside gen_pci_init() when this later function fails.
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@free-electrons.com>
Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>

The patch moves the gen_pci_parse_request_of_pci_ranges() function from
drivers/pci/host/pci-host-common.c into drivers/pci/of.c to easily share
common source code between PCI host drivers.
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@free-electrons.com>
Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>

Clean up drivers/Makefile by moving the pci/endpoint and pci/dwc entries
from drivers/Makefile into drivers/pci/Makefile.

Since we don't want to introduce any dependency between CONFIG_PCI and
CONFIG_PCI_ENDPOINT, we now always execute drivers/pci/Makefile.

Hence all Makefiles in drivers/pci/ were updated accordingly so no file is
compiled when CONFIG_PCI is not defined.

Also, we add a comment to reinforce that EPC and EPF libraries must be
initialized before their users. Hence built-in EPC drivers, such as
those of Designware, are linked after the endpoint core libraries.

Finally, we add another comment to explain why obj-y has been chosen
instead of obj-$(CONFIG_PCIE_DW) to parse the dwc/ sub-folder.
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@free-electrons.com>
Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>

If CONFIG_DEBUG_SLAB=y, and no PCIe card is inserted, the kernel crashes
during probe on r8a7791/koelsch:

  rcar-pcie fe000000.pcie: PCIe link down
  Unable to handle kernel paging request at virtual address 6b6b6b6b

(seeing this message requires earlycon and keep_bootcon).

Indeed, pci_free_host_bridge() frees the PCI host bridge, including the
embedded rcar_pcie object, so pci_free_resource_list() must not be called
afterwards.

To fix this, move the call to pci_free_resource_list() up, and update the
label name accordingly.

Fixes: ddd535f1 ("PCI: rcar: Fix memory leak when no PCIe card is inserted")
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NSimon Horman <horms+renesas@verge.net.au>
Acked-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>

Rename xgene_pcie_probe_bridge() to xgene_pcie_probe() to follow the
convention of other drivers.  No functional change intended.
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>

Rename xilinx_pcie_link_is_up() to xilinx_pcie_link_up() to follow the
convention of other drivers.  No functional change intended.
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: NMichal Simek <michal.simek@xilinx.com>

Rename altera_pcie_link_is_up() to altera_pcie_link_up() to follow the
convention of other drivers.  No functional change intended.
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: NLey Foon Tan <ley.foon.tan@intel.com>

The effective_affinity_mask is always set when an interrupt is assigned in
__assign_irq_vector() -> apic->cpu_mask_to_apicid(), e.g. for struct apic
apic_physflat: -> default_cpu_mask_to_apicid() ->
irq_data_update_effective_affinity(), but it looks d->common->affinity
remains all-1's before the user space or the kernel changes it later.

In the early allocation/initialization phase of an IRQ, we should use the
effective_affinity_mask, otherwise Hyper-V may not deliver the interrupt to
the expected CPU.  Without the patch, if we assign 7 Mellanox ConnectX-3
VFs to a 32-vCPU VM, one of the VFs may fail to receive interrupts.
Tested-by: NAdrian Suhov <v-adsuho@microsoft.com>
Signed-off-by: NDexuan Cui <decui@microsoft.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NJake Oshins <jakeo@microsoft.com>
Cc: stable@vger.kernel.org
Cc: Jork Loeser <jloeser@microsoft.com>
Cc: Stephen Hemminger <sthemmin@microsoft.com>
Cc: K. Y. Srinivasan <kys@microsoft.com>

Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.

By default all files without license information are under the default
license of the kernel, which is GPL version 2.

Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier.  The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.

This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.

How this work was done:

Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
 - file had no licensing information it it.
 - file was a */uapi/* one with no licensing information in it,
 - file was a */uapi/* one with existing licensing information,

Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.

The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne.  Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.

The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed.  Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.

Criteria used to select files for SPDX license identifier tagging was:
 - Files considered eligible had to be source code files.
 - Make and config files were included as candidates if they contained >5
   lines of source
 - File already had some variant of a license header in it (even if <5
   lines).

All documentation files were explicitly excluded.

The following heuristics were used to determine which SPDX license
identifiers to apply.

 - when both scanners couldn't find any license traces, file was
   considered to have no license information in it, and the top level
   COPYING file license applied.

   For non */uapi/* files that summary was:

   SPDX license identifier                            # files
   ---------------------------------------------------|-------
   GPL-2.0                                              11139

   and resulted in the first patch in this series.

   If that file was a */uapi/* path one, it was "GPL-2.0 WITH
   Linux-syscall-note" otherwise it was "GPL-2.0".  Results of that was:

   SPDX license identifier                            # files
   ---------------------------------------------------|-------
   GPL-2.0 WITH Linux-syscall-note                        930

   and resulted in the second patch in this series.

 - if a file had some form of licensing information in it, and was one
   of the */uapi/* ones, it was denoted with the Linux-syscall-note if
   any GPL family license was found in the file or had no licensing in
   it (per prior point).  Results summary:

   SPDX license identifier                            # files
   ---------------------------------------------------|------
   GPL-2.0 WITH Linux-syscall-note                       270
   GPL-2.0+ WITH Linux-syscall-note                      169
   ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause)    21
   ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)    17
   LGPL-2.1+ WITH Linux-syscall-note                      15
   GPL-1.0+ WITH Linux-syscall-note                       14
   ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause)    5
   LGPL-2.0+ WITH Linux-syscall-note                       4
   LGPL-2.1 WITH Linux-syscall-note                        3
   ((GPL-2.0 WITH Linux-syscall-note) OR MIT)              3
   ((GPL-2.0 WITH Linux-syscall-note) AND MIT)             1

   and that resulted in the third patch in this series.

 - when the two scanners agreed on the detected license(s), that became
   the concluded license(s).

 - when there was disagreement between the two scanners (one detected a
   license but the other didn't, or they both detected different
   licenses) a manual inspection of the file occurred.

 - In most cases a manual inspection of the information in the file
   resulted in a clear resolution of the license that should apply (and
   which scanner probably needed to revisit its heuristics).

 - When it was not immediately clear, the license identifier was
   confirmed with lawyers working with the Linux Foundation.

 - If there was any question as to the appropriate license identifier,
   the file was flagged for further research and to be revisited later
   in time.

In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.

Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights.  The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.

Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.

In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.

Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
 - a full scancode scan run, collecting the matched texts, detected
   license ids and scores
 - reviewing anything where there was a license detected (about 500+
   files) to ensure that the applied SPDX license was correct
 - reviewing anything where there was no detection but the patch license
   was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
   SPDX license was correct

This produced a worksheet with 20 files needing minor correction.  This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.

These .csv files were then reviewed by Greg.  Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected.  This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.)  Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: NKate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: NPhilippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

PTR_ERR should access the value just tested by IS_ERR, otherwise the wrong
error code will be returned.

Fixes: 2eeb02b2 ("PCI: faraday: Add clock handling")
Signed-off-by: NWei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>

Add Tegra186 PCIe support.  UPHY programming is performed by BPMP; PHY
enable calls are not required for Tegra186 PCIe.

Power partition ungate is done by BPMP powergate driver.  The Tegra186
DT description must include a "power-domains" property, which results in
dev->pm_domain being set.
Tested-by: NMikko Perttunen <mperttunen@nvidia.com>
Tested-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NManikanta Maddireddy <mmaddireddy@nvidia.com>
[bhelgaas: add "power-domains" reference]
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NMikko Perttunen <mperttunen@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>

Add support for allocating multiple MSIs at the same time, so that the
MSI_FLAG_MULTI_PCI_MSI flag can be added to the msi_domain_info structure.

Avoid storing the hwirq in the low 5 bits of the message data, as it is
used by the device. Also fix an endianness problem by using readl().
Signed-off-by: NSandor Bodo-Merle <sbodomerle@gmail.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NRay Jui <ray.jui@broadcom.com>

The Tegra PCI host controller can generate configuration space accesses
with byte, word and dword granularity for devices. Only root ports can't
have their configuration space accessed in this way.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

struct pci_host_bridge gained hooks to map/swizzle IRQs, so that the IRQ
mapping can be done automatically by PCI core code through the
pci_assign_irq() function instead of resorting to arch-specific
implementation callbacks to carry out the same task which force PCI host
bridge drivers implementation to implement per-arch kludges to carry out a
task that is inherently architecture agnostic.

Commit 769b461f ("arm64: PCI: Drop DT IRQ allocation from
pcibios_alloc_irq()") was assuming all PCI host controller drivers had been
converted to use ->map_irq(), but that wasn't the case: pci-aardvark had
not been converted. Due to this, it broke the support for legacy PCI
interrupts when using the pci-aardvark driver (used on Marvell Armada 3720
platforms).

In order to fix this, we make sure the ->map_irq and ->swizzle_irq fields
of pci_host_bridge are properly filled in.

Fixes: 769b461f ("arm64: PCI: Drop DT IRQ allocation from pcibios_alloc_irq()")
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Cc: stable@vger.kernel.org	# v4.13+

This reverts commit d7bd554f.

It turns out that Tegra20 has a bug in the implementation of the MSI
target address register (which is worked around by the existence of the
struct tegra_pcie_soc.msi_base_shift parameter) that restricts the MSI
target memory to the lower 32 bits of physical memory on that particular
generation. The offending patch causes a regression on TrimSlice, which
is a Tegra20-based device and has a PCI network interface card.

An initial, simpler fix was to change the MSI target address for Tegra20
only, but it was pointed out that the offending commit also prevents the
use of 32-bit only MSI capable devices, even on later chips. Technically
this was never guaranteed to work with the prior code in the first place
because the allocated page could have resided beyond the 4 GiB boundary,
but it is still possible that this could've introduced a regression.

The proper fix that was settled on is to select a fixed address within
the lowest 32 bits of physical address space that is otherwise unused,
but testing of that patch has provided mixed results that are not fully
understood yet.

Given all of the above and the relative urgency to get this fixed in
v4.13, revert the offending commit until a universal fix is found.

Fixes: d7bd554f ("PCI: tegra: Do not allocate MSI target memory")
Reported-by: NTomasz Maciej Nowak <tmn505@gmail.com>
Reported-by: NErik Faye-Lund <kusmabite@gmail.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Cc: stable@vger.kernel.org	# 4.13.x

Some implementations of the Synopsys DesignWare PCIe controller implement
a so-called ECAM shift mode, which allows a static memory window to be
configured that covers the configuration space of the entire bus range.

Usually, when the firmware performs all the low level configuration that is
required to expose this controller in a fully ECAM compatible manner, we
can simply describe it as "pci-host-ecam-generic" and be done with it.
However, in some cases (e.g., the Marvell Armada 80x0 as well as the
Socionext SynQuacer Soc), the IP was synthesized with an ATU window
granularity that does not allow the first bus to be mapped in a way that
prevents the device on the downstream port from appearing more than once,
and so we still need special handling in software to drive this static
almost-ECAM configuration.

So extend the pci-host-generic driver so it can support these controllers
as well, by adding special config space accessors that take the above quirk
into account.

Note that, unlike most drivers for this IP, this driver does not expose a
fake bridge device at B/D/F 00:00.0. There is no point in doing so, given
that this is not a true bridge, and does not require any windows to be
configured in order for the downstream device to operate correctly.
Omitting it also prevents the PCI resource allocation routines from handing
out BAR space to it unnecessarily.
Signed-off-by: NArd Biesheuvel <ard.biesheuvel@linaro.org>
[bhelgaas: factor out pci_dw_valid_device(), add pci_dw_ecam_map_bus() and
use generic read/write functions]
Signed-off-by: NBjorn Helgaas <helgaas@kernel.org>
Acked-by: NWill Deacon <will.deacon@arm.com>

This PCI host bridge from V3 Semiconductor needs no further
introduction. An ancient driver for it has been sitting in
arch/arm/mach-integrator/pci_v3.* since before v2.6.12 and the
initial migration to git.

But we need to get the drivers out of arch/arm/* and get proper handling of
the old drivers, rewrite and clean up so the PCI maintainer can control the
mass of drivers without having to run all over the kernel. We also switch
swiftly to all the new infrastructure found in the PCI hosts as of late.

Some code is preserved so I have added an extensive list of authors in the
top comment section.

This driver probes with the following result:

  OF: PCI: host bridge /pciv3@62000000 ranges:
  OF: PCI:   No bus range found for /pciv3@62000000, using [bus 00-ff]
  OF: PCI:    IO 0x60000000..0x6000ffff -> 0x00000000
  OF: PCI:   MEM 0x40000000..0x4fffffff -> 0x40000000
  OF: PCI:   MEM 0x50000000..0x5fffffff -> 0x50000000
  pci-v3-semi 62000000.pciv3: initialized PCI V3 Integrator/AP integration
  pci-v3-semi 62000000.pciv3: PCI host bridge to bus 0000:00
  pci_bus 0000:00: root bus resource [bus 00-ff]
  pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
  pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
  pci_bus 0000:00: root bus resource [mem 0x50000000-0x5fffffff pref]
  pci-v3-semi 62000000.pciv3: parity error interrupt
  pci-v3-semi 62000000.pciv3: master abort error interrupt
  pci-v3-semi 62000000.pciv3: PCI target LB->PCI READ abort interrupt
  pci-v3-semi 62000000.pciv3: master abort error interrupt
  (repeats a few times)
  pci 0000:00:09.0: [1011:0024] type 01 class 0x060400
  pci-v3-semi 62000000.pciv3: master abort error interrupt
  pci-v3-semi 62000000.pciv3: PCI target LB->PCI READ abort interrupt
  pci 0000:00:0b.0: [8086:1229] type 00 class 0x020000
  pci 0000:00:0b.0: reg 0x10: [mem 0x00000000-0x00000fff pref]
  pci 0000:00:0b.0: reg 0x14: [io  0x0000-0x001f]
  pci 0000:00:0b.0: reg 0x18: [mem 0x00000000-0x000fffff]
  pci 0000:00:0b.0: reg 0x30: [mem 0x00000000-0x000fffff pref]
  pci 0000:00:0b.0: supports D1 D2
  pci 0000:00:0b.0: PME# supported from D0 D1 D2 D3hot
  pci 0000:00:0c.0: [5333:8811] type 00 class 0x030000
  pci 0000:00:0c.0: reg 0x10: [mem 0x00000000-0x03ffffff]
  pci 0000:00:0c.0: reg 0x30: [mem 0x00000000-0x0000ffff pref]
  pci 0000:00:0c.0: vgaarb: VGA device added: decodes=io+mem,owns=io,locks=none
  PCI: bus0: Fast back to back transfers disabled
  PCI: bus1: Fast back to back transfers enabled
  pci 0000:00:0c.0: BAR 0: assigned [mem 0x40000000-0x43ffffff]
  pci 0000:00:0b.0: BAR 2: assigned [mem 0x44000000-0x440fffff]
  pci 0000:00:0b.0: BAR 6: assigned [mem 0x50000000-0x500fffff pref]
  pci 0000:00:0c.0: BAR 6: assigned [mem 0x50100000-0x5010ffff pref]
  pci 0000:00:0b.0: BAR 0: assigned [mem 0x50110000-0x50110fff pref]
  pci 0000:00:0b.0: BAR 1: assigned [io  0x1000-0x101f]
  pci 0000:00:09.0: PCI bridge to [bus 01]
  pci 0000:00:0b.0: Firmware left e100 interrupts enabled; disabling
  (...)
  e100: Intel(R) PRO/100 Network Driver, 3.5.24-k2-NAPI
  e100: Copyright(c) 1999-2006 Intel Corporation
  e100 0000:00:0b.0: enabling device (0146 -> 0147)
  e100 0000:00:0b.0 eth0: addr 0x50110000, irq 31, MAC addr 00:08:c7:99:d2:57

> lspci
  00:0b.0 Class 0200: 8086:1229
  00:09.0 Class 0604: 1011:0024
  00:0c.0 Class 0300: 5333:8811

> cat /proc/iomem
  40000000-4fffffff : V3 PCI NON-PRE-MEM
    40000000-43ffffff : 0000:00:0c.0
    44000000-440fffff : 0000:00:0b.0
      44000000-440fffff : e100
  50000000-5fffffff : V3 PCI PRE-MEM
    50000000-500fffff : 0000:00:0b.0
    50100000-5010ffff : 0000:00:0c.0
    50110000-50110fff : 0000:00:0b.0
      50110000-50110fff : e100
  61000000-61ffffff : /pciv3@62000000
  62000000-6200ffff : /pciv3@62000000
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
[bhelgaas: fold in %pR fixes from Arnd Bergmann <arnd@arndb.de>:
http://lkml.kernel.org/r/20171011140224.3770968-1-arnd@arndb.de]
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
CC: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>

Add support for the MSI controller in Tango, which supports 256
message-signaled interrupts and a single doorbell address.
Signed-off-by: NMarc Gonzalez <marc_gonzalez@sigmadesigns.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Use the new of_pci_dma_range_parser_init() to reduce code duplication.
Signed-off-by: NMarc Gonzalez <marc_gonzalez@sigmadesigns.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>

Use tabs (not spaces) for indentation.  No functional change intended.
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Apparently the PCIe capability is at address 0x40 in config space of X-Gene
v1 Root Ports.  Add a definition of that and use the generic PCI_EXP_RTCTL
offset into the capability.  No functional change intended.
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

When platform_get_irq() fails we should propagate the real error value
instead of always returning -EINVAL.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Cc: Duc Dang <dhdang@apm.com>

When platform_get_irq() fails we should propagate the real error value
instead of always returning -EINVAL.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Cc: Michal Simek <michal.simek@xilinx.com>

When platform_get_irq() fails we should propagate the real error value
instead of always returning -EINVAL.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Cc: Shawn Lin <shawn.lin@rock-chips.com>

platform_get_irq() returns a negative number on failure, so adjust the
logic to detect such condition and propagate the real error value on
failure.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Cc: Ley Foon Tan <lftan@altera.com>

Use tabs (not spaces) for indentation.  No functional change intended.
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

PCI_EXP_CAP is an iProc-specific value, so rename it to IPROC_PCI_EXP_CAP
to make it obvious that it's not related to the generic values like
PCI_EXP_RTCTL, etc.  No functional change intended.
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

During soft reset (e.g., "reboot" from Linux) on some iProc-based SOCs, the
LCPLL clock and PERST both go off simultaneously.  This seems in accordance
with the PCIe Card Electromechanical spec, r2.0, sec 2.2.3, which says the
clock goes inactive after PERST# goes active, but doesn't specify how long
the clock should be valid after PERST#.

However, we have observed that with the iProc Stingray, some Intel NVMe
endpoints, e.g., the P3700 400GB series, are not detected correctly upon
the next boot sequence unless the clock remains valid for some time after
PERST# is asserted.

Delay 500ms after asserting PERST# before performing a reboot.  The 500ms
is experimentally determined.
Signed-off-by: NOza Pawandeep <oza.oza@broadcom.com>
[bhelgaas: changelog, add spec reference, fold in iproc_pcie_shutdown()
export from Arnd Bergmann <arnd@arndb.de>]
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NRay Jui <ray.jui@broadcom.com>
Reviewed-by: NScott Branden <scott.branden@broadcom.com>

Fix various typos and whitespace errors:

  s/Synopsis/Synopsys/
  s/Designware/DesignWare/
  s/Keystine/Keystone/
  s/gpio/GPIO/
  s/pcie/PCIe/
  s/phy/PHY/
  s/confgiruation/configuration/

No functional change intended.
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

VMD hardware has to share its vectors among child devices in its PCI
domain so we should allocate as many as possible rather than just ones
that can be affinitized.

pci_alloc_irq_vectors_affinity() limits the number of affinitized IRQs to
the number of present CPUs (see irq_calc_affinity_vectors()).  But we'd
prefer to have more vectors, even if they aren't distributed across the
CPUs, so use pci_alloc_irq_vectors() instead.
Reported-by: NBrad Goodman <Bradley.Goodman@dell.com>
Signed-off-by: NKeith Busch <keith.busch@intel.com>
[bhelgaas: add irq_calc_affinity_vectors() reference to changelog]
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Switch from using custom INTX_NUM macro to the generic PCI_NUM_INTX definition
for the number of INTx interrupts.
Signed-off-by: NHonghui Zhang <honghui.zhang@mediatek.com>
[bhelgaas: use subject/changelog from similar patches]
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

MT2712 and MT7622's PCIe host controller support MSI, but only 32-bit MSI
addresses are supported. It connects to GIC with the same IRQ number as the
INTx IRQ, so it shares the same IRQ with INTx IRQ.

Add MSI support for MT2712 and MT7622.
Signed-off-by: NHonghui Zhang <honghui.zhang@mediatek.com>
[bhelgaas: changes to follow rcar & tegra: rename to mtk_pcie_msi_alloc(),
add mtk_pcie_msi_free(), free hwirq if irq_create_mapping() fails, call
irq_dispose_mapping() from mtk_msi_teardown_irq()]
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NRyder Lee <ryder.lee@mediatek.com>

75983c6d1f38 ("PCI: mediatek: Add controller support for MT2712 and
MT7622") has put the mtk_pcie * into bus->sysdata.  Take advantage of that
to get the private data and simplify the code.
Signed-off-by: NHonghui Zhang <honghui.zhang@mediatek.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NRyder Lee <ryder.lee@mediatek.com>

MT2712 and MT7622 using a new IP block of Gen2 controller which has two
root ports and shares the same probing flow with MT2701/MT7623.

Both MT2712 and MT7622 have the same per-port control registers, but
there are slight differences between them:

  - MT7622 has more clocks than MT2712.

  - MT7622 has shared control registers which are used to enable LTSSM and
    ASPM while MT2712 does not.

Add host controller support for MT2712/MT7622.
Signed-off-by: NRyder Lee <ryder.lee@mediatek.com>
Signed-off-by: NHonghui Zhang <honghui.zhang@mediatek.com>
[bhelgaas: folded in fix from http://lkml.kernel.org/r/1502715868-17651-2-git-send-email-honghui.zhang@mediatek.com]
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

This is a transitional patch.  We currently use platfarm_get_resource() for
retrieving the IOMEM resources, but there might be some chips don't have
subsys/shared registers part, which depends on platform design, and these
will be introduced in further patches.

Switch this function to use the platform_get_resource_byname() so that the
binding can be agnostic of the resource order.
Signed-off-by: NRyder Lee <ryder.lee@mediatek.com>
Signed-off-by: NHonghui Zhang <honghui.zhang@mediatek.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Introduce a structure "mtk_pcie_soc" to abstract the differences between
controller generations, and the .startup() hook is used to encapsulate some
SoC-dependent related setting.  In doing so, the common code which will be
reused by future chips.
Signed-off-by: NRyder Lee <ryder.lee@mediatek.com>
Signed-off-by: NHonghui Zhang <honghui.zhang@mediatek.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Rename "port->index" to "port->slot" since the ports are hardwired at
PCI_SLOT.  Also rename "mtk_pcie_parse_ports()" to "mtk_pcie_parse_port()"
since it parses one port each time.

No functional change in this patch.
Signed-off-by: NHonghui Zhang <honghui.zhang@mediatek.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>