- 03 11月, 2018 2 次提交
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由 Guo Ren 提交于
The driver is for gx6605s SOC system timer and there are two same timers in gx6605s. We use one for clkevt and another one for clksrc. The timer is mmio map to access, so we need give mmio address in dts. The counter at 0x0 offset is clock event. The counter at 0x40 offset is clock source. Signed-off-by: NGuo Ren <ren_guo@c-sky.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
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由 Guo Ren 提交于
The driver is for C-SKY SMP timer. It only supports oneshot event and 32bit overflow for clocksource. Per cpu core has one timer and all timers share one clock-counter-input from the same clocksource. This use mfcr&mtcr instructions to access the regs. Signed-off-by: NGuo Ren <ren_guo@c-sky.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
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- 13 8月, 2018 1 次提交
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由 Palmer Dabbelt 提交于
The RISC-V ISA defines a per-hart real-time clock and timer, which is present on all systems. The clock is accessed via the 'rdtime' pseudo-instruction (which reads a CSR), and the timer is set via an SBI call. Contains various improvements from Atish Patra <atish.patra@wdc.com>. Signed-off-by: NDmitriy Cherkasov <dmitriy@oss-tech.org> Signed-off-by: NPalmer Dabbelt <palmer@dabbelt.com> [hch: remove dead code, add SPDX tags, used riscv_of_processor_hart(), minor cleanups, merged hotplug cpu support and other improvements from Atish] Signed-off-by: NChristoph Hellwig <hch@lst.de> Acked-by: NThomas Gleixner <tglx@linutronix.de> Reviewed-by: NAtish Patra <atish.patra@wdc.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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- 19 5月, 2018 1 次提交
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由 Chunyan Zhang 提交于
SPRD arch doesn't select SPRD_TIMER, so this config would not appear even if ARCH_SPRD is set but COMPILE_TEST not. Fix the dependency of this config with SPRD arch, and set a default value for it, also leave other choices for EXPERT. Signed-off-by: NChunyan Zhang <chunyan.zhang@spreadtrum.com> Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
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- 31 3月, 2018 1 次提交
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由 Tomer Maimon 提交于
Add Nuvoton BMC NPCM7xx timer driver. The clocksource Enable 24-bit TIMER0 and TIMER1 counters, while TIMER0 serve as clockevent and TIMER1 serve as clocksource. Signed-off-by: NTomer Maimon <tmaimon77@gmail.com> Reviewed-by: NBrendan Higgins <brendanhiggins@xxxxxxxxxx> Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
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- 09 3月, 2018 1 次提交
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由 Masahiro Yamada 提交于
The ATMEL_ST config selects MFD_SYSCON, but does not depend on HAS_IOMEM. Compile testing on architecture without HAS_IOMEM causes "unmet direct dependencies" in Kconfig phase. Detected by "make ARCH=score allyesconfig". Add the proper dependency to the ATMEL_ST config. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NThomas Gleixner <tglx@linutronix.de> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Arnd Bergmann <arnd@arndb.de> Link: https://lkml.kernel.org/r/1520335233-11277-1-git-send-email-yamada.masahiro@socionext.com
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- 23 2月, 2018 2 次提交
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由 James Hogan 提交于
Now that arch/metag/ has been removed, remove the metag generic per-thread timer driver. It is of no value without the architecture code. Signed-off-by: NJames Hogan <jhogan@kernel.org> Acked-by: NDaniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-metag@vger.kernel.org
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由 Keerthy 提交于
Move the dmtimer driver out of plat-omap to clocksource. So that non-omap devices also could use this. No Code changes done to the driver file only renamed to timer-ti-dm.c. Also removed the config dependencies for OMAP_DM_TIMER. Signed-off-by: NKeerthy <j-keerthy@ti.com> Reviewed-by: NSebastian Reichel <sebastian.reichel@collabora.co.uk> Tested-by: NLadislav Michl <ladis@linux-mips.org> [tony@atomide.com: add select omap_dm_timer for omap16xx] Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 22 2月, 2018 1 次提交
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由 Rick Chen 提交于
ATCPIT100 is often used on the Andes architecture, This timer provide 4 PIT channels. Each PIT channel is a multi-function timer, can be configured as 32,16,8 bit timers or PWM as well. For system timer it will set channel 1 32-bit timer0 as clock source and count downwards until underflow and restart again. It also set channel 0 32-bit timer0 as clock event and count downwards until condition match. It will generate an interrupt for handling periodically. Signed-off-by: NRick Chen <rickchen36@gmail.com> Signed-off-by: NGreentime Hu <green.hu@gmail.com> Reviewed-by: NLinus Walleij <linus.walleij@linaro.org> Add andestech atcpit100 timer
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- 09 1月, 2018 2 次提交
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由 Benjamin Gaignard 提交于
Convert the driver to use the timer_of() helpers. This allows the removal of a custom private structure, factors out and simplifies the code. [Daniel Lezcano]: Respin against the critical fix patch and massaged the changelog. Tested-by: NBenjamin Gaignard <benjamin.gaignard@st.com> Signed-off-by: NBenjamin Gaignard <benjamin.gaignard@st.com> Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org> Acked-by: NBenjamin Gaignard <benjamin.gaignard@st.com> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/1515418139-23276-12-git-send-email-daniel.lezcano@linaro.orgSigned-off-by: NIngo Molnar <mingo@kernel.org>
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由 Baolin Wang 提交于
The Spreadtrum SC9860 platform will use the architected timers as local clock events, but we also need a broadcast timer device to wake up the CPUs when the CPUs are in sleep mode. The Spreadtrum timer can support 32-bit or 64-bit counters, as well as supporting period mode or one-shot mode. Signed-off-by: NBaolin Wang <baolin.wang@spreadtrum.com> Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org> Acked-by: NPhilippe Ombredanne <pombredanne@nexb.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/1515418139-23276-8-git-send-email-daniel.lezcano@linaro.org [ Minor readability edits. ] Signed-off-by: NIngo Molnar <mingo@kernel.org>
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- 20 10月, 2017 1 次提交
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由 Arnd Bergmann 提交于
We regularly run into build errors when a clocksource driver selects CONFIG_TIMER_OF while CONFIG_GENERIC_CLOCKEVENTS is disabled: In file included from drivers/clocksource/timer-of.c:25:0: drivers/clocksource/timer-of.h:35:28: error: field 'clkevt' has incomplete type At the moment, three drivers can show this behavior: ARMV7M_SYSTICK, CLKSRC_ST_LPC and CLKSRC_NPS. We could add further dependencies as we did many times, but I have looked a little bit more at what architectures are left that don't use GENERIC_CLOCKEVENTS, and this shows that there is a better solution. On arch/frv and arch/ia64, we never select CONFIG_GENERIC_CLOCKEVENTS and we also don't use ARCH_USES_GETTIMEOFFSET, which would block the clocksource Kconfig menu. On m68k, some platforms use CONFIG_GENERIC_CLOCKEVENTS, some use ARCH_USES_GETTIMEOFFSET, and some use neither of them. The good news is that there is no configuration that does not set CONFIG_GENERIC_CLOCKEVENTS but that wants to enable any of the Kconfig symbols in the menu, so we can simply replace the dependency with the stricter one. While in theory one could have a clocksource driver without the clockevent infrastructure, this seems unlikely to be relevant in the future any more. We can probably drop some of the other dependencies as well now, e.g. there should generally be no reason to depend on CONFIG_ARM unless the driver uses architecture specific assembly. Reported-by: NRandy Dunlap <rdunlap@infradead.org> Signed-off-by: NArnd Bergmann <arnd@arndb.de> Reviewed-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
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- 29 8月, 2017 1 次提交
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由 Dong Aisheng 提交于
IMX Timer/PWM Module (TPM) supports both timer and pwm function while this patch only adds the timer support. PWM would be added later. The TPM counter, compare and capture registers are clocked by an asynchronous clock that can remain enabled in low power modes. NOTE: We observed in a very small probability, the bus fabric contention between GPU and A7 may results a few cycles delay of writing CNT registers which may cause the min_delta event got missed, so we need add a ETIME check here in case it happened. Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Anson Huang <Anson.Huang@nxp.com> Cc: Bai Ping <ping.bai@nxp.com> Signed-off-by: NDong Aisheng <aisheng.dong@nxp.com> Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
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- 11 8月, 2017 1 次提交
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由 Matt Redfearn 提交于
In v4.13, CLKSRC_PISTACHIO can select TIMER_OF on architectures without GENERIC_CLOCKEVENTS, resulting in a struct clock_event_device missing some required features and build breakage compiling timer_of.c. One of the symbols selecting TIMER_OF is CLKSRC_PISTACHIO, so add the dependency on GENERIC_CLOCKEVENTS. Thanks to kbuild test robot for finding this error (https://lkml.org/lkml/2017/7/16/249) Signed-off-by: NMatt Redfearn <matt.redfearn@imgtec.com> Suggested-by: NIan Abbott <abbotti@mev.co.uk> Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
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- 27 6月, 2017 1 次提交
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由 Daniel Lezcano 提交于
Previously a framework to factor out the drivers init function has been merged. Use this common framework in this driver, we get: Before: text data bss dec hex filename 1787 384 12 2183 887 drivers/clocksource/sun4i_timer.o After: text data bss dec hex filename 1407 512 0 1919 77f drivers/clocksource/sun4i_timer.o Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org> Tested-by: NChen-Yu Tsai <wens@csie.org>
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- 19 6月, 2017 1 次提交
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由 Andreas Färber 提交于
The Actions Semi S500 SoC provides four timers, 2Hz0/1 and 32-bit TIMER0/1. Use TIMER0 as clocksource and TIMER1 as clockevents. Based on LeMaker linux-actions tree. An S500 datasheet can be found on the LeMaker Guitar pages: http://www.lemaker.org/product-guitar-download-29.htmlAcked-by: NDaniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: NAndreas Färber <afaerber@suse.de>
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- 14 6月, 2017 3 次提交
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由 Daniel Lezcano 提交于
The different drivers are all using the same pattern when initializing. 1. Get the base address 2. Get the irq number 3. Get the clock 4. Prepare and enable the clock 5. Get the rate 6. Request an interrupt Instead of repeating again and again these steps in all the drivers, let's provide a common init routine to give the opportunity to factor all of them out. We can expect a significant kernel size improvement when the common routine will be used in all the drivers. Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
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由 Daniel Lezcano 提交于
The config option name is now renamed to 'TIMER_ACPI' for consistency with the CLOCKSOURCE_OF_DECLARE => TIMER_OF_DECLARE change. Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Daniel Lezcano 提交于
The config option name is now renamed to 'TIMER_OF' for consistency with the CLOCKSOURCE_OF_DECLARE => TIMER_OF_DECLARE change. Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
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- 12 6月, 2017 2 次提交
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由 Daniel Lezcano 提交于
After discussing it, this feature is dropped as it is not considered adequate: https://patchwork.kernel.org/patch/9639317/ There is no user of this macro yet, so there is no impact on the drivers. This reverts commit 376bc271. Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
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由 Linus Walleij 提交于
This merges the Moxa Art timer driver into the Faraday FTTMR010 driver and replaces all Kconfig symbols to use the Faraday driver instead. We are now so similar that the drivers can be merged by just adding a few lines to the Faraday timer. Differences: - The Faraday driver explicitly sets the counter to count upwards for the clocksource, removing the need for the clocksource core to invert the value. - The Faraday driver also handles sched_clock() On the Aspeed, the counter can only count downwards, so support the timers in downward-counting mode as well, and flag the Aspeed to use this mode. This mode was tested on the Gemini so I have high hopes that it'll work fine on the Aspeed as well. After this we have one driver for all three SoCs and a generic Faraday FTTMR010 timer driver, which is nice. Cc: Joel Stanley <joel@jms.id.au> Cc: Jonas Jensen <jonas.jensen@gmail.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> Reviewed-by: NJoel Stanley <joel@jms.id.au> Tested-by: NJoel Stanley <joel@jms.id.au> Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
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- 07 4月, 2017 3 次提交
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由 Linus Walleij 提交于
After some research it turns out that the "Gemini" timer is actually a generic IP block from Faraday Technology named FTTMR010, so as to not make things too confusing we need to rename the driver and its symbols to make sense. The implementation remains the same in this patch but we fix the copy-paste error in the timer name "nomadik_mtu" as we're at it. Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
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由 Alexander Kochetkov 提交于
The clock supplying the arm-global-timer on the rk3188 is coming from the the cpu clock itself and thus changes its rate everytime cpufreq adjusts the cpu frequency making this timer unsuitable as a stable clocksource and sched clock. The rk3188, rk3288 and following socs share a separate timer block already handled by the rockchip-timer driver. Therefore adapt this driver to also be able to act as clocksource and sched clock on rk3188. In order to test clocksource you can run following commands and check how much time it take in real. On rk3188 it take about ~45 seconds. cpufreq-set -f 1.6GHZ date; sleep 60; date In order to use the patch you need to declare two timers in the dts file. The first timer will be initialized as clockevent provider and the second one as clocksource. The clockevent must be from alive subsystem as it used as backup for the local timers at sleep time. The patch does not break compatibility with older device tree files. The older device tree files contain only one timer. The timer will be initialized as clockevent, as expected. rk3288 (and probably anything newer) is irrelevant to this patch, as it has the arch timer interface. This patch may be useful for Cortex-A9/A5 based parts. Signed-off-by: NAlexander Kochetkov <al.kochet@gmail.com> Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
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由 Marc Zyngier 提交于
Cortex-A73 (all versions) counter read can return a wrong value when the counter crosses a 32bit boundary. The workaround involves performing the read twice, and to return one or the other depending on whether a transition has taken place. Acked-by: NThomas Gleixner <tglx@linutronix.de> Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
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- 08 2月, 2017 5 次提交
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由 Ding Tianhong 提交于
Erratum Hisilicon-161010101 says that the ARM generic timer counter "has the potential to contain an erroneous value when the timer value changes". Accesses to TVAL (both read and write) are also affected due to the implicit counter read. Accesses to CVAL are not affected. The workaround is to reread the system count registers until the value of the second read is larger than the first one by less than 32, the system counter can be guaranteed not to return wrong value twice by back-to-back read and the error value is always larger than the correct one by 32. Writes to TVAL are replaced with an equivalent write to CVAL. Signed-off-by: NDing Tianhong <dingtianhong@huawei.com> [Mark: split patch, fix Kconfig, reword commit message] Signed-off-by: NMark Rutland <mark.rutland@arm.com> Acked-by: NDaniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
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由 Ding Tianhong 提交于
Currently we have code inline in the arch timer probe path to cater for Freescale erratum A-008585, complete with ifdeffery. This is a little ugly, and will get worse as we try to add more errata handling. This patch refactors the handling of Freescale erratum A-008585. Now the erratum is described in a generic arch_timer_erratum_workaround structure, and the probe path can iterate over these to detect errata and enable workarounds. This will simplify the addition and maintenance of code handling Hisilicon erratum 161010101. Signed-off-by: NDing Tianhong <dingtianhong@huawei.com> [Mark: split patch, correct Kconfig, reword commit message] Signed-off-by: NMark Rutland <mark.rutland@arm.com> Acked-by: NDaniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
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由 Chris Brandt 提交于
This patch adds a OSTM driver for the Renesas architecture. The OS Timer (OSTM) has independent channels that can be used as a freerun or interval times. This driver uses the first probed device as a clocksource and then any additional devices as clock events. Signed-off-by: NChris Brandt <chris.brandt@renesas.com> Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
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由 Linus Walleij 提交于
This is a rewrite of the Gemini timer driver in arch/arm/mach-gemini/timer.c trying to do everything the device tree way: - Make every IO-access relative to a base address and dynamic so we can do a dynamic ioremap and get going. - Do not poke around directly in the global syscon registers, access them using the syscon regmap style design pattern for the one register we need to check. - Find register range and interrupt from the device tree. Cc: Janos Laube <janos.dev@gmail.com> Cc: Paulius Zaleckas <paulius.zaleckas@gmail.com> Cc: Hans Ulli Kroll <ulli.kroll@googlemail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
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由 Daniel Lezcano 提交于
The current code uses the CLOCKSOURCE_OF_DECLARE macro to fill the clksrc table with a t-uple (name, init_function). Unfortunately it ends up to the clockevent and the clocksource being both initialized with this macro. It is not a problem by itself but there is not a clear distinction between a clockevent and a clocksource in the code initialization path. Somebody can argue there are the same IP block and the same DT node. But conceptually from the software side, there are two distincts entities and as is they should be initialized separetely. Some drivers which do not have a clocksource end up by using the CLOCKSOURCE_OF_DECLARE macro to declare a clockevent. Another result is the fuzzy organization in the clocksource directory, where the clockevents are implemented in the same file than the clocksources or file labelled timer-something implementing a clocksource. This patch provides another macro to specifically declare a clockevent in the same way than the clocksource and gives the opportunity to write two separate drivers, one for the clocksource and another for the clockevents. Hopefully, that can help to do some housework in the directory, perhaps split the drivers in to entities, for example: - clksrc-rockchip.c - clkevt-rockchip.c Also, it gives the possibility to declare clocksources separately in the DT and then use a clocksource from IP block while while clockevents are used from another IP block. Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
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- 01 12月, 2016 1 次提交
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由 Vineet Gupta 提交于
This adds support for - CONFIG_ARC_TIMERS : legacy 32-bit TIMER0 and TIMER1 which count UP from @CNT to @LIMIT, before optionally triggering an interrupt. These are programmed using ARC auxiliary register interface. These are present in all ARC cores (ARC700 and ARC HS38) TIMER0 serves as clockevent for all ARC linux builds. TIMER1 is used for clocksource in arc700 builds. - CONFIG_ARC_TIMERS_64BIT: 64-bit counters, RTC and GFRC found in ARC HS38 cores. These are independnet IP blocks with different programming model respectively. Link: http://lkml.kernel.org/r/20161111231132.GA4186@maiAcked-by: NDaniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
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- 21 10月, 2016 1 次提交
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由 Rich Felker 提交于
At the hardware level, the J-Core PIT is integrated with the interrupt controller, but it is represented as its own device and has an independent programming interface. It provides a 12-bit countdown timer, which is not presently used, and a periodic timer. The interval length for the latter is programmable via a 32-bit throttle register whose units are determined by a bus-period register. The periodic timer is used to implement both periodic and oneshot clock event modes; in oneshot mode the interrupt handler simply disables the timer as soon as it fires. Despite its device tree node representing an interrupt for the PIT, the actual irq generated is programmable, not hard-wired. The driver is responsible for programming the PIT to generate the hardware irq number that the DT assigns to it. On SMP configurations, J-Core provides cpu-local instances of the PIT; no broadcast timer is needed. This driver supports the creation of the necessary per-cpu clock_event_device instances. A nanosecond-resolution clocksource is provided using the J-Core "RTC" registers, which give a 64-bit seconds count and 32-bit nanoseconds that wrap every second. The driver converts these to a full-range 32-bit nanoseconds count. Signed-off-by: NRich Felker <dalias@libc.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: linux-sh@vger.kernel.org Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Link: http://lkml.kernel.org/r/b591ff12cc5ebf63d1edc98da26046f95a233814.1476393790.git.dalias@libc.orgSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
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- 24 9月, 2016 1 次提交
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由 Scott Wood 提交于
Erratum A-008585 says that the ARM generic timer counter "has the potential to contain an erroneous value for a small number of core clock cycles every time the timer value changes". Accesses to TVAL (both read and write) are also affected due to the implicit counter read. Accesses to CVAL are not affected. The workaround is to reread TVAL and count registers until successive reads return the same value. Writes to TVAL are replaced with an equivalent write to CVAL. The workaround is to reread TVAL and count registers until successive reads return the same value, and when writing TVAL to retry until counter reads before and after the write return the same value. The workaround is enabled if the fsl,erratum-a008585 property is found in the timer node in the device tree. This can be overridden with the clocksource.arm_arch_timer.fsl-a008585 boot parameter, which allows KVM users to enable the workaround until a mechanism is implemented to automatically communicate this information. This erratum can be found on LS1043A and LS2080A. Acked-by: NMarc Zyngier <marc.zyngier@arm.com> Signed-off-by: NScott Wood <oss@buserror.net> [will: renamed read macro to reflect that it's not usually unstable] Signed-off-by: NWill Deacon <will.deacon@arm.com>
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- 16 9月, 2016 1 次提交
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由 Chanwoo Choi 提交于
This patch allows building and compile-testing the driver also for ARM64. The delay_timer is only supported on ARMv7. Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Kukjin Kim <kgene@kernel.org> Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com> Acked-by: NDaniel Lezcano <daniel.lezcano@linaro.org> [k.kozlowski: Adjusted commit msg] Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
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- 28 6月, 2016 7 次提交
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由 Will Deacon 提交于
Disabling the eventstream can be useful for both remotely debugging a deployed production system and development of code using WFE-based polling loops. Whilst this can currently be controlled via a Kconfig option (CONFIG_ARM_ARCH_TIMER_EVTSTREAM), it's often desirable to toggle the feature on the command line, so this patch adds a new command-line option ("clocksource.arm_arch_timer.evtstrm") to do just that. The default behaviour is determined based on CONFIG_ARM_ARCH_TIMER_EVTSTREAM. Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
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由 Daniel Lezcano 提交于
Change the Kconfig option logic to fullfil with the current approach, allowing the user to compile the driver on different platforms. The current option let the user to select the clocksource or not. The Kconfig option policy is to let the platform to select the timer automatically. Add the COMPILE_TEST option, so the prompt to select the driver will be showed only when COMPILE_TEST is set and will let this driver to compile on different platform, thus increasing the compilation test coverage. Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
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由 Daniel Lezcano 提交于
Change the Kconfig option logic to fullfil with the current approach, allowing the user to compile the driver on different platforms. Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
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由 Daniel Lezcano 提交于
Change the Kconfig option logic to fullfil with the current approach, allowing the user to compile the driver on different platforms. Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
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由 Daniel Lezcano 提交于
Change the Kconfig option logic to fullfil with the current approach. A new Kconfig option is added, CONFIG_INTEGRATOR_AP_TIMER and is selected by the platform. Then the clocksource's Kconfig is changed to make this option selectable by the user if the COMPILE_TEST option is set. Otherwise, it is up to the platform's Kconfig to select the timer. Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
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由 Daniel Lezcano 提交于
Change the Kconfig option logic to fullfil with the current approach. A new Kconfig option is added, CONFIG_KEYSTONE_TIMER and is selected by the platform. Then the clocksource's Kconfig is changed to make this option selectable by the user if the COMPILE_TEST option is set. Otherwise, it is up to the platform's Kconfig to select the timer. Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
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由 Daniel Lezcano 提交于
Change the Kconfig option logic to fullfil with the current approach. A new Kconfig option is added, CONFIG_NSPIRE_TIMER and is selected by the platform. Then the clocksource's Kconfig is changed to make this option selectable by the user if the COMPILE_TEST option is set. Otherwise, it is up to the platform's Kconfig to select the timer. Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
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