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  1. 06 4月, 2017 2 次提交
  3. 16 3月, 2017 3 次提交
  5. 15 3月, 2017 2 次提交
  7. 14 3月, 2017 2 次提交
    • J
      drm/tilcdc: Set framebuffer DMA address to HW only if CRTC is enabled · 11abbc9f
      由 Jyri Sarha 提交于 
      Touching HW while clocks are off is a serious error and for instance
breaks suspend functionality. After this patch tilcdc_crtc_update_fb()
always updates the primary plane's framebuffer pointer, increases fb's
reference count and stores vblank event. tilcdc_crtc_update_fb() only
writes the fb's DMA address to HW if the crtc is enabled, as
tilcdc_crtc_enable() takes care of writing the address on enable.

This patch also refactors the tilcdc_crtc_update_fb() a bit. Number of
subsequent small changes had made it almost unreadable. There should
be no other functional changes but checking the CRTC's enable
state. However, the locking goes a bit differently and some of the
redundant checks have been removed in this new version.

The enable_lock should be enough to protect the access to
tilcdc_crtc->enabled. The irq_lock protects the access to last_vblank
and next_fb. The check for vrefresh and last_vblank being valid is
redundant, as the vrefresh should be always valid if the CRTC is
enabled and now last_vblank should be too, because it is initialized
to current time when CRTC raster is enabled. If for some reason the
values are not correctly initialized the division by zero warning is
quite appropriate.
Signed-off-by: NJyri Sarha <jsarha@ti.com>
Reviewed-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      11abbc9f
    • J
      drm/tilcdc: Fix hardcoded fail-return value in tilcdc_crtc_create() · abf8315f
      由 Jyri Sarha 提交于 
      Fix badly hardcoded return return value under fail-label. All goto
branches to the label set the "ret"-variable accordingly.
Signed-off-by: NJyri Sarha <jsarha@ti.com>
Reviewed-by: NGabriel Krisman Bertazi <krisman@collabora.co.uk>
      abf8315f
  9. 13 3月, 2017 4 次提交
  11. 11 3月, 2017 2 次提交
  13. 10 3月, 2017 10 次提交
  15. 09 3月, 2017 12 次提交
  17. 08 3月, 2017 2 次提交
  19. 06 3月, 2017 1 次提交
    • C
      drm/i915/gvt: protect RO and Rsvd bits of virtual vgpu configuration space · c2e04fda
      由 Changbin Du 提交于 
      Per PCI specification, Configuration Register has different types (RO,
RW, RW1C, Rsvd). For RO Register bits are read-only and cannot be
altered by software. For RW1C Register bits indicate status when read.
A Set bit indicates a status event which is Cleared by writing a 1b.
Writing a 0b to RW1C bits has no effect. Reserved Register is for future
implementations, and they are read-only and must return zero when read.

Current vGPU configuration write emulation just copy the value as it is.
So we haven't emulated RO, RW1C and Rsvd Registers correctly. This patch
is following the Spec to correct emulation logic. We add a function
vgpu_cfg_mem_write to wrap the access to vGPU configuration memory.
The write function uses a RW Register bitmap to avoid RO bits be
overwritten, and emulate RW1C behavior for the particular status Register.

v2:
  new = src[i] --> new = src[i] & mask (zhenyu)
Signed-off-by: NChangbin Du <changbin.du@intel.com>
Cc: Xiaoguang Chen <xiaoguang.chen@intel.com>
Cc: Zhiyuan Lv <zhiyuan.lv@intel.com>
Cc: Min He <min.he@intel.com>
Reviewed-by: NZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      c2e04fda