1. 14 6月, 2016 1 次提交
    • A
      drm/i915:bxt: Enable Pooled EU support · 33e141ed
      arun.siluvery@linux.intel.com 提交于
      This mode allows to assign EUs to pools which can process work collectively.
      The command to enable this mode should be issued as part of context initialization.
      
      The pooled mode is global, once enabled it has to stay the same across all
      contexts until HW reset hence this is sent in auxiliary golden context batch.
      Thanks to Mika for the preliminary review and comments.
      
      v2: explain why this is enabled in golden context, use feature flag while
      enabling the support (Chris)
      
      v3: Include only kernel support as userspace support is not available yet.
      
      User space clients need to know when the pooled EU feature is present
      and enabled on the hardware so that they can adapt work submissions.
      Create a new device info flag for this purpose.
      
      Set has_pooled_eu to true in the Broxton static device info - Broxton
      supports the feature in hardware and the driver will enable it by
      default.
      
      We need to add getparam ioctls to enable userspace to query availability of
      this feature and to retrieve min. no of eus in a pool but we will expose
      them once userspace support is available. Opensource users for this feature
      are mesa, libva and beignet.
      
      Beignet team is currently working on adding userspace support.
      
      Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (v2)
      Cc: Winiarski, Michal <michal.winiarski@intel.com>
      Cc: Zou, Nanhai <nanhai.zou@intel.com>
      Cc: Yang, Rong R <rong.r.yang@intel.com>
      Cc: Mika Kuoppala <mika.kuoppala@intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Armin Reese <armin.c.reese@intel.com>
      Cc: Tim Gore <tim.gore@intel.com>
      Signed-off-by: NJeff McGee <jeff.mcgee@intel.com>
      Signed-off-by: NArun Siluvery <arun.siluvery@linux.intel.com>
      Reviewed-by: NMichał Winiarski <michal.winiarski@intel.com>
      Signed-off-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com>
      33e141ed
  2. 23 5月, 2016 4 次提交
  3. 21 5月, 2016 1 次提交
    • D
      drm: Nuke ->vblank_disable_allowed · fcee5906
      Daniel Vetter 提交于
      This was added in
      
      commit 0a3e67a4
      Author: Jesse Barnes <jbarnes@virtuousgeek.org>
      Date:   Tue Sep 30 12:14:26 2008 -0700
      
          drm: Rework vblank-wait handling to allow interrupt reduction.
      
      to stay backwards-compatible with old UMS code that didn't even tell
      the kernel when it did a modeset, so that the kernel could
      save/restore vblank counters. At worst this means vblanks will be
      somewhat funky on a setup that very likely no one still runs.
      
      So let's just nuke it.
      
      Plan B would be to set it unconditionally in drm_vblank_init for kms
      drivers, instead of in each driver separately. So if this patch breaks
      anything please only restore the hunks in drmP.h and drm_irq.c, plus
      add a check for DRIVER_MODESET in drm_vblank_init.
      
      Stumbled over this in a discussion on irc with Chris.
      
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Alex Deucher <alexander.deucher@amd.com>
      Cc: Liviu Dudau <liviu.dudau@arm.com>
      Cc: Russell King <rmk+kernel@arm.linux.org.uk>
      Cc: Thierry Reding <thierry.reding@gmail.com>
      Cc: Eric Anholt <eric@anholt.net>
      Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
      Cc: Inki Dae <inki.dae@samsung.com>
      Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
      Cc: Mark Yao <mark.yao@rock-chips.com>
      Cc: Sascha Hauer <s.hauer@pengutronix.de>
      Cc: Philipp Zabel <p.zabel@pengutronix.de>
      Signed-off-by: NDaniel Vetter <daniel.vetter@intel.com>
      Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
      Acked-by: NLiviu Dudau <Liviu.Dudau@arm.com>
      Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
      Tested-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      fcee5906
  4. 16 5月, 2016 1 次提交
  5. 13 5月, 2016 2 次提交
  6. 12 5月, 2016 1 次提交
  7. 11 5月, 2016 3 次提交
  8. 10 5月, 2016 1 次提交
    • V
      drm/i915: Re-enable GGTT earlier during resume on pre-gen6 platforms · ac840ae5
      Ville Syrjälä 提交于
      Move the intel_enable_gtt() call to happen before we touch the GTT
      during resume. Right now it's done way too late. Before
      commit ebb7c78d ("agp/intel-gtt: Only register fake agp driver for gen1")
      it was actually done earlier on account of also getting called from
      the resume hook of the fake agp driver. With the fake agp driver
      no longer getting registered we must move the call up.
      
      The symptoms I've seen on my 830 machine include lowmem corruption,
      other kinds of memory corruption, and straight up hung machine during
      or just after resume. Not really sure what causes the memory corruption,
      but so far I've not seen any with this fix.
      
      I think we shouldn't really need to call this during init, but we have
      been doing that so I've decided to keep the call. However moving that
      call earlier could be prudent as well. Doing it right after the
      intel-gtt probe seems appropriate.
      
      Also tested this on 946gz,elk,ilk and all seemed quite happy with
      this change.
      
      v2: Reorder init_hw vs. enable_hw functions (Chris)
      
      Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
      Cc: drm-intel-fixes@lists.freedesktop.org
      Fixes: ebb7c78d ("agp/intel-gtt: Only register fake agp driver for gen1")
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1462559755-353-1-git-send-email-ville.syrjala@linux.intel.comReviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      ac840ae5
  9. 09 5月, 2016 1 次提交
  10. 05 5月, 2016 1 次提交
  11. 29 4月, 2016 1 次提交
  12. 28 4月, 2016 2 次提交
    • C
      drm/i915: Unify GPU resets upon shutdown · e7ae86ba
      Chris Wilson 提交于
      Both execlists and legacy need to reset the context (and mode) of the
      GPU before we lose control of the system. By resetting the GPU, we
      revert back to default settings. This simplifies the life of any
      subsequent driver (in particular for virtualized setups) as it does not
      then have to try and recover from an unknown condition. As both paths
      need to reset for the same reason, move the reset to a common point.
      
      This unifies the resets added in a647828a (drm/i915: Also perform gpu
      reset under execlist mode) and 8e96d9c4 (drm/i915: reset the GPU on
      context fini).
      
      v2: Restrict the reset to "modern" gen (where we enable HW contexts) to
      try and avoid leaving the machine in an unusable state with a risky
      reset on older GPU. This should keep the status quo as to who performs
      resets (i.e. currently only GPUs with HW contexts perform a reset on
      shutdown).
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
      CC: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Cc: Mika Kuoppala <mika.kuoppala@intel.com>
      Cc: "Niu, Bing" <bing.niu@intel.com>
      Reviewed-by: NMika Kuoppala <mika.kuoppala@intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1461833819-3991-25-git-send-email-chris@chris-wilson.co.uk
      e7ae86ba
    • V
      drm/i915: Update RAWCLK_FREQ register on VLV/CHV · 19ab4ed3
      Ville Syrjälä 提交于
      I just noticed that VLV/CHV have a RAWCLK_FREQ register just like PCH
      platforms. It lives in the display power well, so we should update it
      when enabling the power well.
      
      Interestingly the BIOS seems to leave it at the reset value (125) which
      doesn't match the rawclk frequency on VLV/CHV (200 MHz). As always with
      these register, the spec is extremely vague what the register does. All
      it says is: "This is used to generate a divided down clock for
      miscellaneous timers in display." Based on a quick test, at least AUX
      and PWM appear to be unaffected by this.
      
      But since the register is there, let's configure it in accordance with
      the spec.
      
      Note that we have to move intel_update_rawclk() to occur before we
      touch the power wells, so that the dev_priv->rawclk_freq is already
      populated when the disp2 enable hook gets called for the first time.
      I think this should be safe to do on other platforms as well.
      
      Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1461768202-17544-1-git-send-email-ville.syrjala@linux.intel.comReviewed-by: NRodrigo Vivi <rodrigo.vivi@intel.com>
      19ab4ed3
  13. 19 4月, 2016 1 次提交
    • J
      drm/i915: Clean up PCI config register handling · e10fa551
      Joonas Lahtinen 提交于
      Do not use magic numbers, do not prefix stuff with "PCI_", do not
      declare registers in implementation files. Also move the PCI
      registers under correct comment in i915_reg.h.
      
      v2:
      - Consistently use BSM (not BDSM or other variants from PRM) (Chris)
      - Also include register address to help identify the register (Chris)
      v3:
      - Refer to register value as *_val instead of *_reg (Chris)
      v4:
      - Make style checker happy
      
      Cc: Jani Nikula <jani.nikula@intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      e10fa551
  14. 01 4月, 2016 1 次提交
  15. 31 3月, 2016 1 次提交
    • J
      drm/i915: Refer to GGTT {,VM} consistently · 72e96d64
      Joonas Lahtinen 提交于
      Refer to the GGTT VM consistently as "ggtt->base" instead of just "ggtt",
      "vm" or indirectly through other variables like "dev_priv->ggtt.base"
      to avoid confusion with the i915_ggtt object itself and PPGTT VMs.
      
      Refer to the GGTT as "ggtt" instead of indirectly through chaining.
      
      As a bonus gets rid of the long-standing i915_obj_to_ggtt vs.
      i915_gem_obj_to_ggtt conflict, due to removal of i915_obj_to_ggtt!
      
      v2:
      - Added some more after grepping sources with Chris
      
      v3:
      - Refer to GGTT VM through ggtt->base consistently instead of ggtt_vm
        (Chris)
      
      v4:
      - Convert all dev_priv->ggtt->foo accesses to ggtt->foo.
      
      v5:
      - Make patch checker happy
      
      Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
      Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      72e96d64
  16. 30 3月, 2016 2 次提交
  17. 23 3月, 2016 1 次提交
  18. 22 3月, 2016 1 次提交
  19. 18 3月, 2016 2 次提交
  20. 17 3月, 2016 12 次提交