1. 13 10月, 2015 1 次提交
    • A
      ACPI: Introduce CPU performance controls using CPPC · 337aadff
      Ashwin Chaugule 提交于
      CPPC stands for Collaborative Processor Performance Controls
      and is defined in the ACPI v5.0+ spec. It describes CPU
      performance controls on an abstract and continuous scale
      allowing the platform (e.g. remote power processor) to flexibly
      optimize CPU performance with its knowledge of power budgets
      and other architecture specific knowledge.
      
      This patch adds a shim which exports commonly used functions
      to get and set CPPC specific controls for each CPU. This enables
      CPUFreq drivers to gather per CPU performance data and use
      with exisiting governors or even allows for customized governors
      which are implemented inside CPUFreq drivers.
      Signed-off-by: NAshwin Chaugule <ashwin.chaugule@linaro.org>
      Reviewed-by: NAl Stone <al.stone@linaro.org>
      Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
      337aadff
  2. 26 9月, 2015 3 次提交
  3. 15 9月, 2015 2 次提交
  4. 04 9月, 2015 1 次提交
    • C
      ipmi: Convert the IPMI SI ACPI handling to a platform device · 0fbcf4af
      Corey Minyard 提交于
      The IPMI SI driver was using direct PNP, but that was not really
      ideal because the IPMI device is a platform device.  There was
      some special handling in the acpi_pnp.c code for making this work,
      but that was breaking ACPI handling for the IPMI SSIF driver.
      
      So without this patch there were significant issues getting the
      SSIF driver to work with ACPI.
      
      So use a platform device for ACPI detection and remove the
      entry from acpi_pnp.c.
      Signed-off-by: NCorey Minyard <cminyard@mvista.com>
      0fbcf4af
  5. 01 9月, 2015 1 次提交
  6. 28 8月, 2015 4 次提交
    • D
      x86, pmem: clarify that ARCH_HAS_PMEM_API implies PMEM mapped WB · 96601adb
      Dan Williams 提交于
      Given that a write-back (WB) mapping plus non-temporal stores is
      expected to be the most efficient way to access PMEM, update the
      definition of ARCH_HAS_PMEM_API to imply arch support for
      WB-mapped-PMEM.  This is needed as a pre-requisite for adding PMEM to
      the direct map and mapping it with struct page.
      
      The above clarification for X86_64 means that memcpy_to_pmem() is
      permitted to use the non-temporal arch_memcpy_to_pmem() rather than
      needlessly fall back to default_memcpy_to_pmem() when the pcommit
      instruction is not available.  When arch_memcpy_to_pmem() is not
      guaranteed to flush writes out of cache, i.e. on older X86_32
      implementations where non-temporal stores may just dirty cache,
      ARCH_HAS_PMEM_API is simply disabled.
      
      The default fall back for persistent memory handling remains.  Namely,
      map it with the WT (write-through) cache-type and hope for the best.
      
      arch_has_pmem_api() is updated to only indicate whether the arch
      provides the proper helpers to meet the minimum "writes are visible
      outside the cache hierarchy after memcpy_to_pmem() + wmb_pmem()".  Code
      that cares whether wmb_pmem() actually flushes writes to pmem must now
      call arch_has_wmb_pmem() directly.
      
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Ingo Molnar <mingo@redhat.com>
      Cc: "H. Peter Anvin" <hpa@zytor.com>
      Reviewed-by: NRoss Zwisler <ross.zwisler@linux.intel.com>
      [hch: set ARCH_HAS_PMEM_API=n on x86_32]
      Reviewed-by: NChristoph Hellwig <hch@lst.de>
      [toshi: x86_32 compile fixes]
      Signed-off-by: NToshi Kani <toshi.kani@hp.com>
      Signed-off-by: NDan Williams <dan.j.williams@intel.com>
      96601adb
    • R
      nd_blk: change aperture mapping from WC to WB · 67a3e8fe
      Ross Zwisler 提交于
      This should result in a pretty sizeable performance gain for reads.  For
      rough comparison I did some simple read testing using PMEM to compare
      reads of write combining (WC) mappings vs write-back (WB).  This was
      done on a random lab machine.
      
      PMEM reads from a write combining mapping:
      	# dd of=/dev/null if=/dev/pmem0 bs=4096 count=100000
      	100000+0 records in
      	100000+0 records out
      	409600000 bytes (410 MB) copied, 9.2855 s, 44.1 MB/s
      
      PMEM reads from a write-back mapping:
      	# dd of=/dev/null if=/dev/pmem0 bs=4096 count=1000000
      	1000000+0 records in
      	1000000+0 records out
      	4096000000 bytes (4.1 GB) copied, 3.44034 s, 1.2 GB/s
      
      To be able to safely support a write-back aperture I needed to add
      support for the "read flush" _DSM flag, as outlined in the DSM spec:
      
      http://pmem.io/documents/NVDIMM_DSM_Interface_Example.pdf
      
      This flag tells the ND BLK driver that it needs to flush the cache lines
      associated with the aperture after the aperture is moved but before any
      new data is read.  This ensures that any stale cache lines from the
      previous contents of the aperture will be discarded from the processor
      cache, and the new data will be read properly from the DIMM.  We know
      that the cache lines are clean and will be discarded without any
      writeback because either a) the previous aperture operation was a read,
      and we never modified the contents of the aperture, or b) the previous
      aperture operation was a write and we must have written back the dirtied
      contents of the aperture to the DIMM before the I/O was completed.
      
      In order to add support for the "read flush" flag I needed to add a
      generic routine to invalidate cache lines, mmio_flush_range().  This is
      protected by the ARCH_HAS_MMIO_FLUSH Kconfig variable, and is currently
      only supported on x86.
      Signed-off-by: NRoss Zwisler <ross.zwisler@linux.intel.com>
      Signed-off-by: NDan Williams <dan.j.williams@intel.com>
      67a3e8fe
    • T
      nfit: Clarify memory device state flags strings · 402bae59
      Toshi Kani 提交于
      ACPI 6.0 NFIT Memory Device State Flags in Table 5-129 defines
      NVDIMM status as follows.  These bits indicate multiple info,
      such as failures, pending event, and capability.
      
        Bit [0] set to 1 to indicate that the previous SAVE to the
        Memory Device failed.
        Bit [1] set to 1 to indicate that the last RESTORE from the
        Memory Device failed.
        Bit [2] set to 1 to indicate that platform flush of data to
        Memory Device failed. As a result, the restored data content
        may be inconsistent even if SAVE and RESTORE do not indicate
        failure.
        Bit [3] set to 1 to indicate that the Memory Device is observed
        to be not armed prior to OSPM hand off. A Memory Device is
        considered armed if it is able to accept persistent writes.
        Bit [4] set to 1 to indicate that the Memory Device observed
        SMART and health events prior to OSPM handoff.
      
      /sys/bus/nd/devices/nmemX/nfit/flags shows this flags info.
      The output strings associated with the bits are "save", "restore",
      "smart", etc., which can be confusing as they may be interpreted
      as positive status, i.e. save succeeded.
      
      Change also the dev_info() message in acpi_nfit_register_dimms()
      to be consistent with the sysfs flags strings.
      Reported-by: NRobert Elliott <elliott@hp.com>
      Signed-off-by: NToshi Kani <toshi.kani@hp.com>
      [ross: rename 'not_arm' to 'not_armed']
      Cc: Ross Zwisler <ross.zwisler@linux.intel.com>
      [djbw: defer adding bit5, HEALTH_ENABLED, for now]
      Signed-off-by: NDan Williams <dan.j.williams@intel.com>
      402bae59
    • S
      ACPI / LPSS: Ignore 10ms delay for Braswell · b00855ae
      Srinidhi Kasagar 提交于
      LPSS devices in Braswell does not need the default 10ms
      d3_delay imposed by PCI specification. Removing this
      unnecessary delay significantly reduces the resume time
      approximately upto 200ms on this platform.
      Signed-off-by: NSrinidhi Kasagar <srinidhi.kasagar@intel.com>
      Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com>
      Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
      b00855ae
  7. 27 8月, 2015 1 次提交
    • J
      ACPI, PCI: Penalize legacy IRQ used by ACPI SCI · 5d0ddfeb
      Jiang Liu 提交于
      Nick Meier reported a regression with HyperV that "
        After rebooting the VM, the following messages are logged in syslog
        when trying to load the tulip driver:
          tulip: Linux Tulip drivers version 1.1.15 (Feb 27, 2007)
          tulip: 0000:00:0a.0: PCI INT A: failed to register GSI
          tulip: Cannot enable tulip board #0, aborting
          tulip: probe of 0000:00:0a.0 failed with error -16
        Errors occur in 3.19.0 kernel
        Works in 3.17 kernel.
      "
      
      According to the ACPI dump file posted by Nick at
      https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1440072
      
      The ACPI MADT table includes an interrupt source overridden entry for
      ACPI SCI:
      [236h 0566  1]                Subtable Type : 02 <Interrupt Source Override>
      [237h 0567  1]                       Length : 0A
      [238h 0568  1]                          Bus : 00
      [239h 0569  1]                       Source : 09
      [23Ah 0570  4]                    Interrupt : 00000009
      [23Eh 0574  2]        Flags (decoded below) : 000D
                                         Polarity : 1
                                     Trigger Mode : 3
      
      And in DSDT table, we have _PRT method to define PCI interrupts, which
      eventually goes to:
              Name (PRSA, ResourceTemplate ()
              {
                  IRQ (Level, ActiveLow, Shared, )
                      {3,4,5,7,9,10,11,12,14,15}
              })
              Name (PRSB, ResourceTemplate ()
              {
                  IRQ (Level, ActiveLow, Shared, )
                      {3,4,5,7,9,10,11,12,14,15}
              })
              Name (PRSC, ResourceTemplate ()
              {
                  IRQ (Level, ActiveLow, Shared, )
                      {3,4,5,7,9,10,11,12,14,15}
              })
              Name (PRSD, ResourceTemplate ()
              {
                  IRQ (Level, ActiveLow, Shared, )
                      {3,4,5,7,9,10,11,12,14,15}
              })
      
      According to the MADT and DSDT tables, IRQ 9 may be used for:
       1) ACPI SCI in level, high mode
       2) PCI legacy IRQ in level, low mode
      So there's a conflict in polarity setting for IRQ 9.
      
      Prior to commit cd68f6bd ("x86, irq, acpi: Get rid of special
      handling of GSI for ACPI SCI"), ACPI SCI is handled specially and
      there's no check for conflicts between ACPI SCI and PCI legagy IRQ.
      And it seems that the HyperV hypervisor doesn't make use of the
      polarity configuration in IOAPIC entry, so it just works.
      
      Commit cd68f6bd gets rid of the specially handling of ACPI SCI,
      and then the pin attribute checking code discloses the conflicts
      between ACPI SCI and PCI legacy IRQ on HyperV virtual machine,
      and rejects the request to assign IRQ9 to PCI devices.
      
      So penalize legacy IRQ used by ACPI SCI and mark it unusable if ACPI
      SCI attributes conflict with PCI IRQ attributes.
      
      Please refer to following links for more information:
      https://bugzilla.kernel.org/show_bug.cgi?id=101301
      https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1440072
      
      Fixes: cd68f6bd ("x86, irq, acpi: Get rid of special handling of GSI for ACPI SCI")
      Reported-and-tested-by: NNick Meier <nmeier@microsoft.com>
      Acked-by: NThomas Gleixner <tglx@linutronix.de>
      Cc: 3.19+ <stable@vger.kernel.org> # 3.19+
      Signed-off-by: NJiang Liu <jiang.liu@linux.intel.com>
      Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
      5d0ddfeb
  8. 26 8月, 2015 19 次提交
  9. 25 8月, 2015 4 次提交
  10. 15 8月, 2015 1 次提交
  11. 14 8月, 2015 1 次提交
    • H
      ACPI / video: Fix circular lock dependency issue in the video-detect code · 7231ed1a
      Hans de Goede 提交于
      Before this commit, the following would happen:
      
       a) acpi_video_get_backlight_type() gets called
       b) acpi_video_get_backlight_type() calls acpi_video_init_backlight_type()
       c) acpi_video_init_backlight_type() locks its function static init_mutex
       d) acpi_video_init_backlight_type() calls backlight_register_notifier()
       e) backlight_register_notifier() takes its notifier-chain lock
      
      And when the backlight notifier chain gets called we've:
      
       1) blocking_notifier_call_chain() gets called
       2) blocking_notifier_call_chain() takes the notifier-chain lock
       3) blocking_notifier_call_chain() calls acpi_video_backlight_notify()
       4) acpi_video_backlight_notify() calls acpi_video_get_backlight_type()
       5) acpi_video_get_backlight_type() calls acpi_video_init_backlight_type()
       6) acpi_video_init_backlight_type() locks its function static init_mutex
      
      So in the first call sequence we have:
      
       a) init_mutex gets locked
       b) notifier-chain gets locked
      
      and in the second call sequence we have:
      
       1) notifier-chain gets locked
       2) init_mutex gets locked
      
      And we've a circular locking dependency. This specific locking dependency
      is fixable without using the big hammer otherwise known as a workqueue,
      but further analysis shows a similar problem with the backlight notifier
      chain lock vs register_count_mutex from drivers/acpi/acpi_video.c,
      and fixing that becomes problematic.
      
      So this commit simply fixes this with the big hammer, performance
      wise this is a non issue as we expect the work to get scheduled
      exactly zero or one times during normal system use.
      
      Fixes: 93a291df (ACPI / video: Move backlight notifier to video_detect.c)
      Signed-off-by: NHans de Goede <hdegoede@redhat.com>
      Reported-and-tested-by: NSedat Dilek <sedat.dilek@gmail.com>
      Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
      7231ed1a
  12. 13 8月, 2015 2 次提交