The tegra_output_exit() and tegra_output_remove() functions cannot fail,
so make them return void.
Signed-off-by: NThierry Reding <treding@nvidia.com>

The tegra_output midlayer is now completely gone and output drivers use
it purely as a helper library.
Signed-off-by: NThierry Reding <treding@nvidia.com>

The debugfs cleanup code never fails, so no error is returned. Therefore
the functions can all return void instead.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Implement encoder and connector within the eDP driver itself using the
Tegra output helpers rather than using the Tegra output as midlayer. By
doing so one level of indirection is removed and output drivers become
more flexible while keeping the majority of the advantages provided by
the common output helpers.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Implement encoder and connector within the DSI driver itself using the
Tegra output helpers rather than using the Tegra output as midlayer. By
doing so one level of indirection is removed and output drivers become
more flexible while keeping the majority of the advantages provided by
the common output helpers.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Implement encoder and connector within the HDMI driver itself using the
Tegra output helpers rather than using the Tegra output as midlayer. By
doing so one level of indirection is removed and output drivers become
more flexible while keeping the majority of the advantages provided by
the common output helpers.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Implement encoder and connector within the RGB driver itself using the
Tegra output helpers rather than using the Tegra output as midlayer. By
doing so one level of indirection is removed and output drivers become
more flexible while keeping the majority of the advantages provided by
the common output helpers.
Signed-off-by: NThierry Reding <treding@nvidia.com>

This is a small helper that performs the basic steps required by all
output drivers to prepare the display controller for use with a given
encoder.
Signed-off-by: NThierry Reding <treding@nvidia.com>

In order to transition output drivers to using the struct tegra_output
as a helper rather than midlayer, make this callback optional. Instead
drivers should implement the equivalent as part of ->mode_fixup(). For
the conversion to atomic modesetting a new callback ->atomic_check()
should be implemented that updates the display controller's state with
the corresponding parent clock, rate and shift clock divider.
Signed-off-by: NThierry Reding <treding@nvidia.com>

The output layer was initially designed to help reduce the amount of
code duplicated in output drivers. An unfortunate side-effect of that
was that it turned into a midlayer and it became difficult to make the
output drivers work without bending over backwards to fit into the
midlayer.

This commit starts to convert the midlayer into a helper library by
exporting most of the common functions so that they can be used by the
output drivers directly. Doing so will allow output drivers to reuse
common code paths but more easily override them where necessary.
Signed-off-by: NThierry Reding <treding@nvidia.com>

The DRM core should take care of disabling all unneeded planes, so there
is no need to do this explicitly.
Signed-off-by: NThierry Reding <treding@nvidia.com>

This structure will be extended using non-framebuffer related callbacks
in subsequent patches, so it should move to a more central location.
Signed-off-by: NThierry Reding <treding@nvidia.com>

When disabling the display controller, stop it and wait for it to become
idle. Doing so ensures that no further accesses to the framebuffer occur
and the buffers can be safely unmapped or freed.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Previously output drivers would all stop the display controller in their
disable path. However with the transition to atomic modesetting the
display controller needs to be kept running until all planes have been
disabled so that software can properly determine (using VBLANK counts)
when it is safe to remove the framebuffers associated with the planes.

Moving this code into the display controller's disable path also gets
rid of the duplication of this into all output drivers.
Signed-off-by: NThierry Reding <treding@nvidia.com>

All output drivers have open-coded variants of this function, so export
it to remove some code duplication.
Signed-off-by: NThierry Reding <treding@nvidia.com>

kfree(ERR_PTR(-ENOMEM)) will not work very well.
Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

We can't save two values to the IRQ flags at the same time so the IRQs
are not enabled at the end.  This kind of bug is easy to miss in testing
if the function is normally called with IRQs disabled so we wouldn't
enable IRQs anyway.
Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Compliance testing shows that HS Trail is off by -12%. Increase the HS
Trail time to make this test pass.
Signed-off-by: NDavid Ung <davidu@nvidia.com>
[treding@nvidia.com: update specification references, add comment]
Signed-off-by: NThierry Reding <treding@nvidia.com>

This allows a DRM driver unload/reload cycle to completely reset the DSI
controller and may help in situations where it's broken.
Signed-off-by: NThierry Reding <treding@nvidia.com>

This reset is necessary to properly clean up the internal state of the
controller.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Use a sized unsigned 32-bit data type (u32) to store register contents.
The DSI registers are 32 bits wide irrespective of the architecture's
data width.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Use a sized unsigned 32-bit data type (u32) to store register contents.
The HDMI registers are 32 bits wide irrespective of the architecture's
data width.
Signed-off-by: NThierry Reding <treding@nvidia.com>

This prevents the compiler from warning about using a variable that is
possibly uninitialized.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Most of the display controller's registers are double-buffered, a few of
them are triple-buffered. The ASSEMBLY shadow copy is latched intto the
ACTIVE copy for double-buffered registers. For triple-buffered registers
the ASSEMBLY copy is first latched into the ARM copy.

Latching into the ACTIVE copy happens immediately if the controller is
inactive. Otherwise the latching happens on the next frame boundary. The
latching of the ASSEMBLY into the ARM copy happens immediately. Latching
is controlled by a set of *_ACT_REQ and *_UPDATE bits in the
DC_CMD_STATE_CONTROL register.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Tegra114 and earlier support specifying the color of the border (i.e.
the active area of the screen that is not covered by any of the overlay
windows). By default this is set to a light blue, so set it to black to
comply with the requirements set by atomic modesetting.
Signed-off-by: NThierry Reding <treding@nvidia.com>

iommu_domain_alloc() returns NULL on error, it never returns error
pointers.
Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The possible_crtcs mask needs to be a mask of CRTC indices. There is no
guarantee that the DRM indices match the hardware pipe number, so the
mask must be computed from the CRTC index.
Signed-off-by: NThierry Reding <treding@nvidia.com>

The DRM core now zeroes out the memory associated with CRTC, encoder and
connector objects upon cleanup, so there's no need to explicitly do that
in drivers anymore.
Signed-off-by: NThierry Reding <treding@nvidia.com>

The iommu_map_sg() function is now available in the IOMMU API, so drop
the open-coded variant.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Previously the struct bus_type exported by the host1x infrastructure was
only a very basic skeleton. Turn that implementation into a more full-
fledged bus to support proper probe ordering and power management.

Note that the bus infrastructure needs to be available before any of the
drivers can be registered. This is automatically ensured if all drivers
are built as loadable modules (via symbol dependencies). If all drivers
are built-in there are no such guarantees and the link order determines
the initcall ordering. Adjust drivers/gpu/Makefile to make sure that the
host1x bus infrastructure is initialized prior to any of its users (only
drm/tegra currently).

v2: Fix building host1x and tegra-drm as modules
Reported-by: NDave Airlie <airlied@gmail.com>
Reviewed-by: NSean Paul <seanpaul@chromium.org>
Reviewed-by: NMark Zhang <markz@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

In finish pageflip, the driver was not selecting the root window when
dispatching events. This exposed a race where a plane update would
change the window selection and cause tegra_dc_finish_page_flip to check
the wrong base address.

This patch also protects access to the window selection register as well
as the registers affected by it.
Signed-off-by: NSean Paul <seanpaul@chromium.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

If the requested buffer size wasn't a multiple of the page size, the
IOMMU code would round down the size to the next multiple of the page
size, thereby causing translation errors. To fix this we no longer pass
around the requested size but reuse the computed size of the GEM object.
This is already rounded to the next page boundary, so mapping that size
works out fine.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Buffers obtained via shmem may still have associated cachelines. If they
aren't properly flushed they may cause framebuffer corruption if the
cache gets flushed after the application has drawn to it.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Page-flip completion could race with page-flip submission, so extend the
critical section to include all accesses to page-flip related data.
Reported-by: NAlexandre Courbot <acourbot@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The hardware pipe numbers don't always match the DRM CRTC indices. This
can happen for example if the first display controller defers probe,
causing it to be registered with DRM after the second display
controller. When that happens the hardware pipe numbers and DRM CRTC
indices become different. Make sure that the CRTC index is always used
when accessing per-CRTC VBLANK data. This can be ensured by using the
drm_crtc_vblank_*() API, which will do the right thing automatically
given a struct drm_crtc *.
Signed-off-by: NThierry Reding <treding@nvidia.com>

The ->load_lut() callback is optional, therefore a dummy implementation
is not needed.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

dma_free_writecombine() must not be called on a buffer that couldn't be
allocated. Check for a valid virtual address before attempting to free
the memory to avoid a crash.
Reported-by: NSean Paul <seanpaul@chromium.org>
Reviewed-by: NSean Paul <seanpaul@chromium.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

This helps in determining what errors happened at specifics points in
the initialization sequence.
Signed-off-by: NThierry Reding <treding@nvidia.com>

When fbdev initialization fails, make sure to unreference the GEM
objects properly. Note that we can't do this in the general error
unwinding path because ownership of the GEM object references is
transferred to the framebuffer upon creation.
Signed-off-by: NThierry Reding <treding@nvidia.com>

When the DRM device is torn down and the connector is removed, make sure
to detach the panel to make sure there are no dangling pointers.
Signed-off-by: NThierry Reding <treding@nvidia.com>