1. 30 8月, 2013 1 次提交
  2. 23 8月, 2013 2 次提交
  3. 22 8月, 2013 3 次提交
  4. 21 8月, 2013 3 次提交
  5. 14 8月, 2013 1 次提交
    • C
      gianfar: Add flow control support · 23402bdd
      Claudiu Manoil 提交于
      eTSEC has Rx and Tx flow control capabilities that may be enabled
      through MACCFG1[Rx_Flow, Tx_Flow] bits.  These bits must not be set
      however when eTSEC is operated in Half-Duplex mode.  Unfortunately,
      the driver currently sets these bits unconditionally.
      This patch adds the proper handling of the PAUSE frame capability
      register bits by implementing the ethtool -A interface.  When pause
      autoneg is enabled, the controller uses the phy's capability to
      negotiate PAUSE frame settings with the link partner and reconfigures
      its Rx_Flow and Tx_Flow settings to match the capabilities of the
      link partner.  If pause autoneg is off, the PAUSE frame generation
      may be forced manually (ethtool -A).  Flow control is disabled by
      default now.
      This implementation is inspired by the tg3 driver.
      Signed-off-by: NLutz Jaenicke <ljaenicke@innominate.com>
      Signed-off-by: NClaudiu Manoil <claudiu.manoil@freescale.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      23402bdd
  6. 06 8月, 2013 2 次提交
    • C
      gianfar: Cleanup TxFCB insertion on xmit · 0d0cffdc
      Claudiu Manoil 提交于
      Cleanup gfar_start_xmit()'s fast path by factoring out "redundant"
      FCB insertion code (repeated gfar_add_fcb() calls and related)
      and by reducing the number of if() clauses (i.e. if(fcb) checks).
      Improve maintainability (e.g. there's less code and easier to read)
      also by introducing do_csum and do_vlan to mark the other 2 Tx TOE
      functionalities, following the same model as do_tstamp.
      fcb_len may also be 0 now, to mark that Tx FCB insertion conditions
      (do_csum, do_vlan, do_tstamp) have not been met.
      Signed-off-by: NClaudiu Manoil <claudiu.manoil@freescale.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      0d0cffdc
    • C
      gianfar: Fix Tx csum generation errata handling · 02d88fb4
      Claudiu Manoil 提交于
      Both [eTSEC76] and [eTSEC12] errata relate to Tx checksum generation
      (for some MPC83xx and MCP8548 older revisions). They require the same
      workaround: manual checksum computation and insertion, and disabling
      the H/W Tx csum acceleration feature (per frame) through Tx FCB
      (Frame Control Block) csum offload settings.
      
      The workaround for [eTSEC76] needs to be fixed because it currently
      fails to disable H/W Tx csum insertion via FCB. This patch fixes it
      and provides a common workaround implementation for both Tx csum errata.
      Signed-off-by: NClaudiu Manoil <claudiu.manoil@freescale.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      02d88fb4
  7. 02 8月, 2013 1 次提交
  8. 31 7月, 2013 1 次提交
  9. 28 7月, 2013 1 次提交
    • F
      net: fec: workaround stop tx during errata ERR006358 · 03191656
      Frank Li 提交于
      If the ready bit in the transmit buffer descriptor (TxBD[R])
      is previously detected as not set during a prior frame transmission,
      then the ENET_TDAR[TDAR] bit is cleared at a later time, even if
      additional TxBDs were added to the ring and the ENET_TDAR[TDAR]
      bit is set. This results in frames not being transmitted until
      there is a 0-to-1 transition on ENET_TDAR[TDAR].
      
      Workarounds:
      code can use the transmit frame interrupt flag (ENET_EIR[TXF])
      as a method to detect whether the ENET has completed transmission
      and the ENET_TDAR[TDAR] has been cleared. If ENET_TDAR[TDAR] is
      detected as cleared when packets are queued and waiting for transmit,
      then a write to the TDAR bit will restart TxBD processing.
      
      This case main happen when loading is light. A ethernet package may
      not send out utile next package put into tx queue.
      
      How to test:
      while [ true ]
      do
      	ping <IP> -s 10000 -w 4
      	ping <IP> -s 6000 -w 2
      	ping <IP> -s 4000 -w 2
      	ping <IP> -s 10000 -w 2
      done
      
      You will see below result in overnight test.
      
      6008 bytes from 10.192.242.116: seq=1 ttl=128 time=0.722 ms
      4008 bytes from 10.192.242.116: seq=0 ttl=128 time=1001.008 ms
      4008 bytes from 10.192.242.116: seq=1 ttl=128 time=1.010 ms
      10008 bytes from 10.192.242.116: seq=0 ttl=128 time=0.896 ms
      
      After apply this patch, >1000ms delay disappear.
      Signed-off-by: NFrank Li <Frank.Li@freescale.com>
      Acked-by: NFugang Duan  <B38611@freescale.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      03191656
  10. 24 7月, 2013 1 次提交
  11. 23 7月, 2013 6 次提交
  12. 04 7月, 2013 1 次提交
  13. 03 7月, 2013 1 次提交
  14. 02 7月, 2013 2 次提交
  15. 27 6月, 2013 1 次提交
  16. 20 6月, 2013 2 次提交
    • B
      net: Move MII out from under NET_CORE and hide it · a1606c7d
      Ben Hutchings 提交于
      All drivers that select MII also need to select NET_CORE because MII
      depends on it.  This is a bit ridiculous because NET_CORE is just a
      menu option that doesn't enable any code by itself.
      
      There is also no need for it to be a visible option, since its users
      all select it.
      Signed-off-by: NBen Hutchings <ben@decadent.org.uk>
      Acked-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      a1606c7d
    • G
      net: fec: Fix build for MCF5272 · d1391930
      Guenter Roeck 提交于
      Commits 4c09eed9 (net: fec: Enable imx6 enet checksum acceleration) and
      baa70a5c (net: fec: enable pause frame to improve rx prefomance for 1G
      network) introduced functionality into the FEC driver which is not
      supported on MCF5272. The registers used to implement this functionality
      do not exist on MCF5272. Since register defines for MCF5272 are separate
      from register defines for other chips, building images for MCF5272 fails
      as follows.
      
      fec_main.c: In function 'fec_restart':
      fec_main.c:520:8: error: 'FEC_RACC' undeclared (first use in this function)
      fec_main.c:585:3: error: 'FEC_R_FIFO_RSEM' undeclared (first use in this function)
      fec_main.c:586:3: error: 'FEC_R_FIFO_RSFL' undeclared (first use in this function)
      fec_main.c:587:3: error: 'FEC_R_FIFO_RAEM' undeclared (first use in this function)
      fec_main.c:588:3: error: 'FEC_R_FIFO_RAFL' undeclared (first use in this function)
      fec_main.c:591:3: error: 'FEC_OPD' undeclared (first use in this function)
      
      Adding the missing register defines is not an option, since the registers
      do not exist on MCF5272. Disable the added functionality for MCF5272 builds.
      
      Cc: Frank Li <Frank.Li@freescale.com>
      Cc: Jim Baxter <jim_baxter@mentor.com>
      Signed-off-by: NGuenter Roeck <linux@roeck-us.net>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      d1391930
  17. 18 6月, 2013 1 次提交
  18. 12 6月, 2013 2 次提交
  19. 08 6月, 2013 1 次提交
  20. 05 6月, 2013 1 次提交
  21. 28 5月, 2013 6 次提交