The 'arm,armv8' compatible string is only for software models. It adds
little value otherwise and is inconsistently used as a fallback on some
platforms. Remove it from those platforms.

This fixes warnings generated by the DT schema.
Reported-by: NMichal Simek <michal.simek@xilinx.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Acked-by: NAntoine Tenart <antoine.tenart@bootlin.com>
Acked-by: NNishanth Menon <nm@ti.com>
Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com>
Acked-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: NChanho Min <chanho.min@lge.com>
Acked-by: NKrzysztof Kozlowski <krzk@kernel.org>
Acked-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: NGregory CLEMENT <gregory.clement@bootlin.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Acked-by: NHeiko Stuebner <heiko@sntech.de>
Acked-by: NSimon Horman <horms+renesas@verge.net.au>
Acked-by: NTero Kristo <t-kristo@ti.com>
Acked-by: NWei Xu <xuwei5@hisilicon.com>
Acked-by: NLiviu Dudau <liviu.dudau@arm.com>
Acked-by: NMatthias Brugger <matthias.bgg@gmail.com>
Acked-by: NMichal Simek <michal.simek@xilinx.com>
Acked-by: NScott Branden <scott.branden@broadcom.com>
Acked-by: NKevin Hilman <khilman@baylibre.com>
Acked-by: NChunyan Zhang <zhang.lyra@gmail.com>
Acked-by: NRobert Richter <rrichter@cavium.com>
Acked-by: NJisheng Zhang <Jisheng.Zhang@synaptics.com>
Acked-by: NDinh Nguyen <dinguyen@kernel.org>
Signed-off-by: NRob Herring <robh@kernel.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

The MPP52 signal is on the seconds GPIO instance of CP0, which
corresponds to the &cp0_gpio2 handle.

Rename the property name to the standard '-gpios' suffix while at it.

Fixes: b83e1669 ("arm64: dts: marvell: mcbin: add support for PCIe")
Signed-off-by: NBaruch Siach <baruch@tkos.co.il>
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>

The memory area [0x4000000-0x4200000[ is occupied by the PSCI firmware. Any
attempt to access it from Linux leads to an immediate crash.

So let's make the same memory reservation as the vendor kernel.

[gregory: added as comment that this region matches the mainline U-boot]
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>

The AP6212 is based on the Broadcom BCM43430 or BCM43438. The WiFi side
identifies as BCM43430, while the Bluetooth side identifies as BCM43438.

The Bluetooth side is connected to UART1 in a 4 wire configuration. Same
as the WiFi side, due to being the same chip and package, DLDO2 provides
overall power via VBAT, and DLDO4 provides I/O power via VDDIO. The RTC
clock output provides the LPO low power clock at 32.768 kHz.

This patch enables Bluetooth on this board, and also adds the missing
LPO clock on the WiFi side. There is also a PCM connection for Bluetooth,
but this is not covered here.
Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: NChen-Yu Tsai <wens@csie.org>

The "num-lanes" property for PCIe is not used, remove it.
Signed-off-by: NHonghui Zhang <honghui.zhang@mediatek.com>
Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>

TM2(e) boards have a Broadcom Bluetooth chip connected to 3rd UART port.
Add a device tree node describing it and its resources (control GPIO lines
and clock).
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>

The external nWDOG signal connects to the EVK board reset circuit.

Tested on the i.MX8MQ EVK rev B3.
Signed-off-by: NBaruch Siach <baruch@tkos.co.il>
Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
Signed-off-by: NAbel Vesa <abel.vesa@nxp.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Signed-off-by: NBaruch Siach <baruch@tkos.co.il>
Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
Signed-off-by: NAbel Vesa <abel.vesa@nxp.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

This is the evaluation kit board for the i.MX8M. The current level of
support yields a working console and is able to boot userspace from
SD card or Network.
Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> (v1)
Reviewed-by: Rob Herring <robh@kernel.org> (v3)
Tested-by: Tested-by: Baruch Siach <baruch@tkos.co.il> (v1)
Reviewed-by: NDong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: NAbel Vesa <abel.vesa@nxp.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

This adds the basic DTS for the i.MX8MQ.
For now only the following peripherals are supported:
- IOMUXC (pin controller)
- CCM (clock controller)
- GPIO
- UART
- uSDHC (SD/eMMC controller)
- FEC (ethernet controller)
- i2c

This is enough to get a very basic board support up and running.

One known limitation is that the driver for the GPC interrupt
controller is still missing, rendering the CPU sleep states unusable
as there is nothing waking them up anymore.
Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
Reviewed-by: NDong Aisheng <Aisheng.dong@nxp.com>
Signed-off-by: NAbel Vesa <abel.vesa@nxp.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

We will move the FSL QSPI driver to the SPI framework soon. To
prepare and to make sure the full buswidth is used (as it is with
the current driver), let's add the right properties.
Signed-off-by: NFrieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

The properties 'num-cs' and 'bus-num' were never read by the driver
and can be removed.
Signed-off-by: NFrieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Enable McSPI0 of main domain and add DT node for the SPI NOR flash
connected to CS0.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Signed-off-by: NTero Kristo <t-kristo@ti.com>

There are 3 instances of McSPI in MCU domain and 4 instances in Main domain.
Add DT nodes for all McSPI instances present on AM654 SoC.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Signed-off-by: NTero Kristo <t-kristo@ti.com>

Populate power-domain property for UART nodes, this is required for
Linux to enable UART clocks via PM calls. Without this UART instances
not initialized by bootloader (like main_uart1) fails to work in Linux.
Also, drop current-speed property from main_uart1 and main_uart2 nodes
as these UARTs are not initialized before Linux boots up and current
speed is unknown.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Signed-off-by: NTero Kristo <t-kristo@ti.com>

Enable ECAP PWM which is used for LCD backlight.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Signed-off-by: NTero Kristo <t-kristo@ti.com>

Add DT entry for ECAP0 PWM node present in main domain
Signed-off-by: NVignesh R <vigneshr@ti.com>
Signed-off-by: NTero Kristo <t-kristo@ti.com>

Add DT entries for I2C instances present in AM654 SoC.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Acked-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NTero Kristo <t-kristo@ti.com>

Add pinmux for main uart0 that is serves as console on AM654 EVM
Signed-off-by: NVignesh R <vigneshr@ti.com>
Acked-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NTero Kristo <t-kristo@ti.com>

Add pinctrl regions for the main and wkup mmr.

The range for main pinctrl region contains a gap
at offset 0x2e4, and because of this, the pinctrl
range is split into two sections.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Signed-off-by: NVignesh R <vigneshr@ti.com>
Acked-by: NNishanth Menon <nm@ti.com>

Add node for IMEM clock controller, necessary for Security SubSystem
(SSS) on Exynos5433.
Signed-off-by: NKamil Konieczny <k.konieczny@partner.samsung.com>
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>

A typo in the adv7180 DT node prevents successful probing of the VIN.
Fix it.

Fixes: 6a0942c2 ("arm64: dts: renesas: draak: Describe CVBS input")
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: NJacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add on-board LED support for Rock960 board based on the following
standard used by rest of the 96Boards:

green:user1  default-trigger: heartbeat
green:user2  default-trigger: mmc0/disk-activity(onboard-storage)
green:user3  default-trigger: mmc1 (SD-card)
green:user4  default-trigger: none, panic-indicator
yellow:wlan  default-trigger: phy0tx
blue:bt      default-trigger: hci0-power
Signed-off-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add on-board LED support for Ficus board based on the following
standard used by other 96Boards:

red:user1  default-trigger: heartbeat
red:user2  default-trigger: mmc0/disk-activity (onboard-storage)
red:user3  default-trigger: mmc1 (SD-card)
red:user4  default-trigger: none, panic-indicator
red:wlan   default-trigger: phy0tx
red:bt     default-trigger: hci0-power
Signed-off-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.

Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.

Update cooling maps to include all devices affected by individual trip
points.
Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Enable the USB3 peripheral that is wired to CON2 on the Clearfog GT-8K
board.
Signed-off-by: NBaruch Siach <baruch@tkos.co.il>
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>

Add DT support for the Macchiatobin Single Shot board from SolidRun,
which is similar to the Double Shot board, but does not have the
10G 3310 PHYs - the two ethernet ports are instead connected directly
to the SFP+ cages.
Signed-off-by: NRussell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>

The ESPRESSObin board has a emmc interface available on U11: declare it
and let the bootloader enable it if the emmc is present.

[gregory.clement@bootlin.com: disable the emmc by default]
Signed-off-by: NDing Tao <miyatsu@qq.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>

add the qDMA device tree nodes for LS1046A devices.
Signed-off-by: NWen He <wen.he_1@nxp.com>
Signed-off-by: NPeng Ma <peng.ma@nxp.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

add the qDMA device tree nodes for LS1043A devices.
Signed-off-by: NWen He <wen.he_1@nxp.com>
Signed-off-by: NPeng Ma <peng.ma@nxp.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

LS1088A has a 48-bit address size so make sure that the
dma-ranges property reflects this.
Signed-off-by: NIoana Radulescu <ruxandra.radulescu@nxp.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

The fsl-mc node should sit under the soc node, so move it to
its proper location.

Fixes: ac7c9ff7 ("arm64: dts: ls1088a: add fsl-mc hardware resource manager node")
Signed-off-by: NIoana Radulescu <ruxandra.radulescu@nxp.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.

Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.

Update cooling maps to include all devices affected by individual trip
points.
Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

LS1028A contains two ARM v8 CortexA72 processor cores
with 32 KB L1-D cache and 48 KB L1-I cache

Features summary
 Two 32-bit / 64-bit ARM v8 Cortex-A72 CPUs
  - Arranged as single clusters of two cores sharing a 1 MB L2 cache
  - Speed Up to 1.3 GHz
  - Support for cluster power-gating.
 Cache coherent interconnect (CCI-400)
  - Hardware-managed data coherency
  - Up to 400 MHz
 32-bit DDR4 SDRAM memory controller with ECC
 Two PCIe 3.0 controllers
 One serial ATA (SATA 3.0) controller
 Two high-speed USB 3.0 controllers with integrated PHY

 Following levels of DTSI/DTS files have been created for the LS1028A
  SoC family:

         - fsl-ls1028a.dtsi:
                 DTS-Include file for NXP LS1028A SoC.

         - fsl-ls1028a-qds.dts:
                 DTS file for NXP LS1028A QDS board.

         - fsl-ls1028a-rdb.dts:
                 DTS file for NXP LS1028A RDB board
Signed-off-by: NSudhanshu Gupta <sudhanshu.gupta@nxp.com>
Signed-off-by: NRai Harninder <harninder.rai@nxp.com>
Signed-off-by: NBhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Acked-by: NLi Yang <leoyang.li@nxp.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Removed the wrong compatible string "snps,dw-pcie", in case
match incorrect driver.
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Add the status property disable the PCIe, the property will be enable
by bootloader.
Signed-off-by: NBao Xiaowei <xiaowei.bao@nxp.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

LS1012A-FRWY is an ls1012a based SoC board.
Key features of this board are  Micro SD, USB 3.0,
upto 1GB DDR, UART
Signed-off-by: NPramod Kumar <pramod.kumar_1@nxp.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

A long running stress test on a custom board shipping an AXG SoCs and a
Realtek RTL8211F PHY revealed that after a few hours the connection
speed would drop drastically, from ~1000Mbps to ~3Mbps. At the same time
the 'macirq' (eth0) IRQ would stop being triggered at all and as
consequence the GMAC IRQs never ACKed.

After a painful investigation the problem seemed to be due to a wrong
defined IRQ type for the GMAC IRQ that should be LEVEL_HIGH instead of
EDGE_RISING.

The change in the macirq IRQ type also solved another long standing
issue affecting this SoC/PHY where EEE was causing the network
connection to die after stressing it with iperf3 (even though much
sooner). It's now possible to remove the 'eee-broken-1000t' quirk as
well.

Fixes: feb3cbea ("ARM64: dts: meson-gxbb-odroidc2: fix GbE tx link breakage")
Fixes: 6d28d577 ("ARM64: dts: meson-axg: fix ethernet stability issue")
Reviewed-by: NJerome Brunet <jbrunet@baylibre.com>
Tested-by: NJerome Brunet <jbrunet@baylibre.com>
Acked-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NCarlo Caione <ccaione@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Enable the GPIO interrupt controller for the AXG SoCs.
Signed-off-by: NCarlo Caione <ccaione@baylibre.com>
Reviewed-by: NJerome Brunet <jbrunet@baylibre.com>
Tested-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Now that the GPIO controller has been enabled also on AXG we can hook up
the GPIO interrupt for the PHY.
Tested-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NCarlo Caione <ccaione@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>