1. 07 2月, 2007 2 次提交
    • A
      [MIPS] Make I8259A_IRQ_BASE customizable · 2fa7937b
      Atsushi Nemoto 提交于
      Move I8259A_IRQ_BASE from asm/i8259.h to asm/mach-generic/irq.h and
      make it really customizable.  And remove I8259_IRQ_BASE declared on
      some platforms.  Currently only NEC_CMBVR4133 is using custom
      I8259A_IRQ_BASE value.
      Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp>
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      2fa7937b
    • A
      [MIPS] Define MIPS_CPU_IRQ_BASE in generic header · 97dcb82d
      Atsushi Nemoto 提交于
      The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all
      platforms and are same value on most platforms (0 or 16, depends on
      CONFIG_I8259).  Define them in asm-mips/mach-generic/irq.h and make
      them customizable.  This will save a few cycle on each CPU interrupt.
      
      A good side effect is removing some dependencies to MALTA in generic
      SMTC code.
      
      Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq
      mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing
      them might cause some header dependency problem and there seems no
      good reason to customize it.  So currently only VR41XX is using custom
      MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259.
      
      Testing this patch on those platforms is greatly appreciated.  Thank
      you.
      Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp>
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      97dcb82d
  2. 31 1月, 2007 1 次提交
    • H
      [PATCH] mm: mremap correct rmap accounting · 701dfbc1
      Hugh Dickins 提交于
      Nick Piggin points out that page accounting on MIPS multiple ZERO_PAGEs
      is not maintained by its move_pte, and could lead to freeing a ZERO_PAGE.
      
      Instead of complicating that move_pte, just forget the minor optimization
      when mremapping, and change the one thing which needed it for correctness
      - filemap_xip use ZERO_PAGE(0) throughout instead of according to address.
      
      [ "There is no block device driver one could use for XIP on mips
         platforms" - Carsten Otte ]
      Signed-off-by: NHugh Dickins <hugh@veritas.com>
      Cc: Nick Piggin <nickpiggin@yahoo.com.au>
      Cc: Andrew Morton <akpm@osdl.org>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Carsten Otte <cotte@de.ibm.com>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      701dfbc1
  3. 25 1月, 2007 3 次提交
  4. 24 1月, 2007 1 次提交
    • R
      [MIPS] SMTC: Instant IPI replay. · ac8be955
      Ralf Baechle 提交于
      SMTC pseudo-interrupts between TCs are deferred and queued if the target
      TC is interrupt-inhibited (IXMT). In the first SMTC prototypes, these
      queued IPIs were serviced on return to user mode, or on entry into the
      kernel idle loop. The INSTANT_REPLAY option dispatches them as part of
      local_irq_restore() processing, which adds runtime overhead (hence the
      option to turn it off), but ensures that IPIs are handled promptly even
      under heavy I/O interrupt load.
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      ac8be955
  5. 09 1月, 2007 2 次提交
  6. 14 12月, 2006 2 次提交
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  11. 07 12月, 2006 2 次提交
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  13. 03 12月, 2006 1 次提交
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  15. 30 11月, 2006 5 次提交