1. 09 1月, 2019 1 次提交
  2. 03 1月, 2019 1 次提交
  3. 02 1月, 2019 4 次提交
  4. 28 12月, 2018 1 次提交
  5. 13 12月, 2018 2 次提交
  6. 05 12月, 2018 1 次提交
    • T
      drm/i915: Record GT workarounds in a list · 00936779
      Tvrtko Ursulin 提交于
      To enable later verification of GT workaround state at various stages of
      driver lifetime, we record the list of applicable ones per platforms to a
      list, from which they are also applied.
      
      The added data structure is a simple array of register, mask and value
      items, which is allocated on demand as workarounds are added to the list.
      
      This is a temporary implementation which later in the series gets fused
      with the existing per context workaround list handling. It is separated at
      this stage since the following patch fixes a bug which needs to be as easy
      to backport as possible.
      
      Also, since in the following patch we will be adding a new class of
      workarounds (per engine) which can be applied from interrupt context, we
      straight away make the provision for safe read-modify-write cycle.
      
      v2:
       * Change dev_priv to i915 along the init path. (Chris Wilson)
       * API rename. (Chris Wilson)
      
      v3:
       * Remove explicit list size tracking in favour of growing the allocation
         in power of two chunks. (Chris Wilson)
      
      v4:
       Chris Wilson:
       * Change wa_list_finish to early return.
       * Copy workarounds using the compiler for static checking.
       * Do not bother zeroing unused entries.
       * Re-order struct i915_wa_list.
      
      v5:
       * kmalloc_array.
       * Whitespace cleanup.
      Signed-off-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com>
      Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      Link: https://patchwork.freedesktop.org/patch/msgid/20181203133319.10174-1-tvrtko.ursulin@linux.intel.com
      (cherry picked from commit 25d140fa)
      Fixes: 59b449d5 ("drm/i915: Split out functions for different kinds of workarounds")
      Signed-off-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      00936779
  7. 04 12月, 2018 4 次提交
  8. 29 11月, 2018 1 次提交
  9. 09 11月, 2018 4 次提交
  10. 06 11月, 2018 1 次提交
  11. 02 11月, 2018 1 次提交
  12. 31 10月, 2018 1 次提交
  13. 30 10月, 2018 2 次提交
  14. 24 10月, 2018 1 次提交
  15. 12 10月, 2018 1 次提交
  16. 02 10月, 2018 1 次提交
  17. 27 9月, 2018 1 次提交
  18. 26 9月, 2018 1 次提交
  19. 14 9月, 2018 4 次提交
  20. 13 9月, 2018 1 次提交
  21. 06 9月, 2018 2 次提交
  22. 20 8月, 2018 1 次提交
    • I
      drm/i915: Verify power domains after enabling them · 6dfc4a8f
      Imre Deak 提交于
      After
      commit 2cd9a689 ("drm/i915: Refactor intel_display_set_init_power() logic")
      it makes more sense to check the power domain/well refcounts after
      enabling the power domains functionality. Before that it's guaranteed
      that most power wells (in the INIT domain) will have a reference held,
      so not an interesting state.
      
      While at it also add the check after the init_hw/fini_hw, disable and
      suspend/resume steps. Make the test optional on a Kconfig option since
      it may add substantial overhead: on VLV/CHV the corresponding PUNIT reg
      access for each power well may take up to 20ms.
      
      v2:
      - Add the state check to more spots. (Chris)
      
      v3:
      - During suspend check the state before deiniting display core.
        Afterwards DC states are disabled (and so the dc_off power well is
        enabled) even though we don't hold a reference on it.
      - Do the test conditionally based on a new Kconfig option. (Chris)
      
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      [Add DRM_I915_DEBUG_RUNTIME_PM to welcome messages]
      Signed-off-by: NImre Deak <imre.deak@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20180817145837.26592-1-imre.deak@intel.com
      6dfc4a8f
  23. 16 8月, 2018 2 次提交
  24. 15 8月, 2018 1 次提交