1. 11 12月, 2018 1 次提交
  2. 10 12月, 2018 1 次提交
  3. 27 11月, 2018 1 次提交
    • S
      net/mlx5: EQ, Introduce atomic notifier chain subscription API · 0f597ed4
      Saeed Mahameed 提交于
      Use atomic_notifier_chain to fire firmware events at internal mlx5 core
      components such as eswitch/fpga/clock/FW tracer/etc.., this is to
      avoid explicit calls from low level mlx5_core to upper components and to
      simplify the mlx5_core API for future developments.
      
      Simply provide register/unregister notifiers API and call the notifier
      chain on firmware async events.
      
      Example: to subscribe to a FW event:
      struct mlx5_nb port_event;
      
      MLX5_NB_INIT(&port_event, port_event_handler, PORT_CHANGE);
      mlx5_eq_notifier_register(mdev, &port_event);
      
      where:
       - port_event_handler is the notifier block callback.
       - PORT_EVENT is the suffix of MLX5_EVENT_TYPE_PORT_CHANGE.
      
      The above will guarantee that port_event_handler will receive all FW
      events of the type MLX5_EVENT_TYPE_PORT_CHANGE.
      
      To receive all FW/HW events one can subscribe to
      MLX5_EVENT_TYPE_NOTIFY_ANY.
      
      The next few patches will start moving all mlx5 core components to use
      this new API and cleanup mlx5_eq_async_int misx handler from component
      explicit calls and specific logic.
      Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
      0f597ed4
  4. 13 11月, 2018 1 次提交
  5. 04 10月, 2018 1 次提交
    • F
      net/mlx5: Add Fast teardown support · fcd29ad1
      Feras Daoud 提交于
      Today mlx5 devices support two teardown modes:
      1- Regular teardown
      2- Force teardown
      
      This change introduces the enhanced version of the "Force teardown" that
      allows SW to perform teardown in a faster way without the need to reclaim
      all the pages.
      
      Fast teardown provides the following advantages:
      1- Fix a FW race condition that could cause command timeout
      2- Avoid moving to polling mode
      3- Close the vport to prevent PCI ACK to be sent without been scatter
      to memory
      Signed-off-by: NFeras Daoud <ferasda@mellanox.com>
      Reviewed-by: NMajd Dibbiny <majd@mellanox.com>
      Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
      fcd29ad1
  6. 05 9月, 2018 1 次提交
  7. 09 8月, 2018 1 次提交
  8. 24 7月, 2018 1 次提交
    • F
      net/mlx5: FW tracer, events handling · c71ad41c
      Feras Daoud 提交于
      The tracer has one event, event 0x26, with two subtypes:
      - Subtype 0: Ownership change
      - Subtype 1: Traces available
      
      An ownership change occurs in the following cases:
      1- Owner releases his ownership, in this case, an event will be
      sent to inform others to reattempt acquire ownership.
      2- Ownership was taken by a higher priority tool, in this case
      the owner should understand that it lost ownership, and go through
      tear down flow.
      
      The second subtype indicates that there are traces in the trace buffer,
      in this case, the driver polls the tracer buffer for new traces, parse
      them and prepares the messages for printing.
      
      The HW starts tracing from the first address in the tracer buffer.
      Driver receives an event notifying that new trace block exists.
      HW posts a timestamp event at the last 8B of every 256B block.
      Comparing the timestamp to the last handled timestamp would indicate
      that this is a new trace block. Once the new timestamp is detected,
      the entire block is considered valid.
      
      Block validation and parsing, should be done after copying the current
      block to a different location, in order to avoid block overwritten
      during processing.
      Signed-off-by: NFeras Daoud <ferasda@mellanox.com>
      Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
      c71ad41c
  9. 19 7月, 2018 1 次提交
  10. 20 6月, 2018 1 次提交
  11. 01 6月, 2018 2 次提交
  12. 25 5月, 2018 1 次提交
  13. 17 5月, 2018 2 次提交
  14. 06 4月, 2018 1 次提交
  15. 31 3月, 2018 1 次提交
    • T
      net/mlx5e: Use linear SKB in Striding RQ · 619a8f2a
      Tariq Toukan 提交于
      Current Striding RQ HW feature utilizes the RX buffers so that
      there is no wasted room between the strides. This maximises
      the memory utilization.
      This prevents the use of build_skb() (which requires headroom
      and tailroom), and demands to memcpy the packets headers into
      the skb linear part.
      
      In this patch, whenever a set of conditions holds, we apply
      an RQ configuration that allows combining the use of linear SKB
      on top of a Striding RQ.
      
      To use build_skb() with Striding RQ, the following must hold:
      1. packet does not cross a page boundary.
      2. there is enough headroom and tailroom surrounding the packet.
      
      We can satisfy 1 and 2 by configuring:
      	stride size = MTU + headroom + tailoom.
      
      This is possible only when:
      a. (MTU - headroom - tailoom) does not exceed PAGE_SIZE.
      b. HW LRO is turned off.
      
      Using linear SKB has many advantages:
      - Saves a memcpy of the headers.
      - No page-boundary checks in datapath.
      - No filler CQEs.
      - Significantly smaller CQ.
      - SKB data continuously resides in linear part, and not split to
        small amount (linear part) and large amount (fragment).
        This saves datapath cycles in driver and improves utilization
        of SKB fragments in GRO.
      - The fragments of a resulting GRO SKB follow the IP forwarding
        assumption of equal-size fragments.
      
      Some implementation details:
      HW writes the packets to the beginning of a stride,
      i.e. does not keep headroom. To overcome this we make sure we can
      extend backwards and use the last bytes of stride i-1.
      Extra care is needed for stride 0 as it has no preceding stride.
      We make sure headroom bytes are available by shifting the buffer
      pointer passed to HW by headroom bytes.
      
      This configuration now becomes default, whenever capable.
      Of course, this implies turning LRO off.
      
      Performance testing:
      ConnectX-5, single core, single RX ring, default MTU.
      
      UDP packet rate, early drop in TC layer:
      
      --------------------------------------------
      | pkt size | before    | after     | ratio |
      --------------------------------------------
      | 1500byte | 4.65 Mpps | 5.96 Mpps | 1.28x |
      |  500byte | 5.23 Mpps | 5.97 Mpps | 1.14x |
      |   64byte | 5.94 Mpps | 5.96 Mpps | 1.00x |
      --------------------------------------------
      
      TCP streams: ~20% gain
      Signed-off-by: NTariq Toukan <tariqt@mellanox.com>
      Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
      619a8f2a
  16. 27 3月, 2018 1 次提交
    • I
      net/mlx5e: Expose PFC stall prevention counters · 2fcb12df
      Inbar Karmy 提交于
      Add the needed capability bit and counters to device spec description.
      Expose the following two counters in ethtool:
      
      tx_pause_storm_warning_events: when the device is stalled for a period
      longer than a pre-configured watermark, the counter increase, allowing
      the debug utility an insight into current device status.
      
      tx_pause_storm_error_events: when the device is stalled for a period
      longer than a pre-configured timeout, the pause transmission is disabled,
      and the counter increase.
      Signed-off-by: NInbar Karmy <inbark@mellanox.com>
      Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
      2fcb12df
  17. 15 3月, 2018 1 次提交
  18. 09 1月, 2018 2 次提交
  19. 29 12月, 2017 1 次提交
    • Y
      IB/mlx5: Extend UAR stuff to support dynamic allocation · 31a78a5a
      Yishai Hadas 提交于
      This patch extends the alloc context flow to be prepared for working
      with dynamic UAR allocations.
      
      Currently upon alloc context there is some fix size of UARs that are
      allocated (named 'static allocation') and there is no option to user
      application to ask for more or control which UAR will be used by which
      QP.
      
      In this patch the driver prepares its data structures to manage both the
      static and the dynamic allocations and let the user driver knows about
      the max value of dynamic blue-flame registers that are allowed.
      
      Downstream patches from this series will enable the dynamic allocation
      and the association as part of QP creation.
      Signed-off-by: NYishai Hadas <yishaih@mellanox.com>
      Signed-off-by: NLeon Romanovsky <leon@kernel.org>
      Signed-off-by: NJason Gunthorpe <jgg@mellanox.com>
      31a78a5a
  20. 05 11月, 2017 2 次提交
  21. 28 9月, 2017 1 次提交
  22. 03 9月, 2017 1 次提交
  23. 24 8月, 2017 1 次提交
  24. 24 7月, 2017 2 次提交
  25. 27 6月, 2017 1 次提交
    • I
      net/mlx5: FPGA, Add SBU infrastructure · a9956d35
      Ilan Tayari 提交于
      Add interface to initialize and interact with Innova FPGA SBU
      connections.
      A client driver may use these functions to set up a high-speed DMA
      connection with its SBU hardware logic, and send/receive messages
      over this connection.
      
      A later patch in this patchset will make use of these functions for
      Innova IPSec offload in mlx5 Ethernet driver.
      
      Add commands to retrieve Innova FPGA SBU capabilities, and to
      read/write Innova FPGA configuration space registers and memory,
      over internal I2C.
      
      At high level, the FPGA configuration space is divided such:
       0x00000000 - 0x007fffff is reserved for the SBU
       0x00800000 - 0xffffffff is reserved for the Shell
      0x400000000 - ...        is DDR memory
      
      A later patchset will add support for accessing FPGA CrSpace and memory
      over a high-speed connection. This is the reason for the ACCESS_TYPE
      enumeration, which currently only supports I2C.
      Signed-off-by: NIlan Tayari <ilant@mellanox.com>
      Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
      a9956d35
  26. 22 6月, 2017 1 次提交
  27. 23 5月, 2017 1 次提交
  28. 14 5月, 2017 1 次提交
    • I
      net/mlx5: FPGA, Add basic support for Innova · e29341fb
      Ilan Tayari 提交于
      Mellanox Innova is a NIC with ConnectX and an FPGA on the same
      board. The FPGA is a bump-on-the-wire and thus affects operation of
      the mlx5_core driver on the ConnectX ASIC.
      
      Add basic support for Innova in mlx5_core.
      
      This allows using the Innova card as a regular NIC, by detecting
      the FPGA capability bit, and verifying its load state before
      initializing ConnectX interfaces.
      
      Also detect FPGA fatal runtime failures and enter error state if
      they ever happen.
      
      All new FPGA-related logic is placed in its own subdirectory 'fpga',
      which may be built by selecting CONFIG_MLX5_FPGA.
      This prepares for further support of various Innova features in later
      patchsets.
      Additional details about hardware architecture will be provided as
      more features get submitted.
      Signed-off-by: NIlan Tayari <ilant@mellanox.com>
      Reviewed-by: NBoris Pismenny <borisp@mellanox.com>
      Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
      e29341fb
  29. 06 2月, 2017 1 次提交
  30. 20 1月, 2017 6 次提交