power-isa-version and power-isa-* are cpu node general properties defined
in ePAPR.

If the power-isa-version property exists, then for each category from the
Categories section of Book I of the Power ISA version indicated, the
existence of a property named power-isa-[CAT], where [CAT] is the
abbreviated category name with all uppercase letters converted to
lowercase, indicates that the category is supported by the implementation.

The patch update all e500v2 platforms.
Signed-off-by: NLiu Yu <yu.liu@freescale.com>
Signed-off-by: NOlivia Yin <hong-hua.yin@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Utilize new split between board & SoC, and new SoC device trees split
into pre & post utilizing 'template' includes for SoC IP blocks.

Other changes include:
* Moved to specifying interrupt-parent for mpic at root
* Moved to 4-cell mpic interrupt cells to support MPIC timers
* Dropping "fsl,p1010-IP..." from compatibles for standard blocks
* PCI interrupt map - wrong IRQs for PCI-0 controller
* SDHC interrupt sense was wrong
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Utilize new split between board & SoC, and new SoC device trees split
into pre & post utilizing 'template' includes for SoC IP blocks.

Other changes include:
* Moved to a standard 2 #address-cells & #size-cells at top-level
* Moved to specifying interrupt-parent for mpic at root
* Moved to 4-cell mpic interrupt cells to support MPIC timers
* Removed CPU properties setup by u-boot to match other .dts
* Added localbus node, but no chipselect details at this point
* Reworked PCIe nodes to allow supportin IRQs for controller (errors)
  and moved PCI device IRQs down to virtual bridge level
* Moved mdio nodes up one level instead of under tsec nodes
* Updated ethernet 'model' to 'eTSEC' as that's what on MPC8544
* Dropping "fsl,mpc8544-IP..." from compatibles for standard blocks
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Utilize new split between board & SoC, and new SoC device trees split
into pre & post utilizing 'template' includes for SoC IP blocks.

Other changes include:
* Moved to specifying interrupt-parent for mpic at root
* Moved to 4-cell mpic interrupt cells to support MPIC timers
* Added localbus node, but no chipselect details at this point
* Reworked PCIe nodes to allow supportin IRQs for controller (errors)
* and moved
  PCI device IRQs down to virtual bridge level
* Moved mdio nodes up one level instead of under tsec nodes
* Added GPIO controller node to MPC8536 SoC template
  [ marked as MPC8572 compatiable to get errata handling that applies ]
* Added missing cache-line-size & cache-size properties missing from
  L2-cache node
* Added IP level IEEE 1588 / ptp timer node
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Introduce some common components that we can utilize to build up the
various PQ3/85xx device trees.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>